Noise resistant small signal sensing circuit for a memory device

A sensing circuit having a sensing node electrically coupled to a memory cell and reference node electrically coupled to a reference level, the sensing circuit comprising:

• a differential amplifier having first and second differential input and output nodes;
• a switching circuit having first and second switching input and output terminals, and a clock node at which a first clock signal is applied, the switching circuit electrically coupled to the differential input and output nodes and, in accordance with the first clock signal, switching the coupling of the first and second switching input nodes to a respective differential input node and switching the coupling of the first and second switching output nodes to a respective differential output node;
• first and second capacitors electrically coupled to a respective switching output node;
• a clocked comparator having an output node, a clock node at which a second clock signal is applied, and first and second input nodes electrically coupled to a respective capacitor, in response to the second clock signal, the clocked comparator generating an output signal having a logic state based on the relative voltage levels of the first and second capacitors;
• and
• a current source having first and second current output nodes electrically coupled to a respective capacitor, the current source switching the coupling of each current output node to a respective capacitor based on the logic state of the output signal of the clocked comparator.

A sensing circuit, comprising:

• a first integrator circuit having a first integrator input electrically coupled to a reference level, a second integrator input to which an input is applied, and first and second integrator outputs at which first and second output signals are provided, respectively, the integrator circuit further having an amplifier circuit having pairs of differential input and output nodes, the integrator circuit periodically switching the electrical coupling of each of the differential input nodes to a respective integrator input and the electrical coupling of each of the differential output nodes to a respective integrator output;
• a second integrator circuit having first and second integrator inputs coupled to a respective integrator output of the first integrator circuit and first and second integrator outputs;
• a comparator having first and second input nodes electrically coupled to a respective integrator output of the second integrator circuit and further having an output node, the clocked comparator periodically comparing voltage levels of the first and second input nodes and generating an output signal having a logic state based therefrom;
• and
• a current source having a first pair of current output nodes coupled to a respective integrator output of the first integrator circuit, and further having a second pair of current output nodes coupled to a respective integrator output of the second integrator circuit, the current source switching the coupling of each current output node of the first pair to a respective integrator output of the first integrator circuit, and each current output node of the second pair to a respective integrator output of the second integrator circuit based on the logic state of the output signal of the comparator.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a control circuit coupled to the control bus;
• an MRAM array coupled to the address decoder and control circuit, the MRAM array having a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
• and;
• a read/write circuit coupled to the data bus and the MRAM array, the read/write circuit including sensing circuits coupled to the bit lines, each sensing circuit comprising:
• an integrator circuit having a first integrator input electrically coupled to a reference level, a second integrator input coupled to a respective bit line, and first and second integrator outputs at which first and second output signals are provided, respectively, the integrator circuit further having an amplifier circuit having pairs of differential input and output nodes, the integrator circuit periodically switching the electrical coupling of each of the differential input nodes to a respective integrator input and the electrical coupling of each of the differential output nodes to a respective integrator output;
• a comparator having first and second input nodes electrically coupled to a respective integrator output and further having an output node, the clocked comparator periodically comparing voltage levels of the first and second input nodes and generating an output signal having a logic state based therefrom;
• and
• a current source having first and second current output nodes coupled to a respective integrator output, the current source switching the coupling of each current output node to a integrator output based on the logic state of the output signal of the comparator.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, the memory device comprising,
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a control circuit coupled to the control bus;
• an MRAM array coupled to the address decoder and control circuit, the MRAM array having a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged in rows and columns, each memory cell in a respective row being coupled to a corresponding word line and each memory cell in respective column being coupled to a corresponding bit line;
• and;
• a read/write circuit coupled to the data bus and the MRAM array, the read/write circuit including sensing circuits coupled to the bit lines, each sensing circuit comprising:
• an integrator circuit having a first integrator input electrically coupled to a reference level, a second integrator input coupled to a respective bit line, and first and second integrator outputs at which first and second output signals are provided, respectively, the integrator circuit further having an amplifier circuit having pairs of differential input and output nodes, the integrator circuit periodically switching the electrical coupling of each of the differential input nodes to a respective integrator input and the electrical coupling of each of the differential output nodes to a respective integrator output;
• a comparator having first and second input nodes electrically coupled to a respective integrator output and further having an output node, the clocked comparator periodically comparing voltage levels of the first and second input nodes and generating an output signal having a logic state based therefrom;
• and
• a current source having first and second current output nodes coupled to a respective integrator output, the current source switching the coupling of each current output node to a integrator output based on the logic state of the output signal of the comparator.

A method of sensing a data state of a memory cell, comprising:

• coupling input and output terminals of an integrator circuit according to a first configuration for a first portion of a first time period;
• coupling the input and output terminals of the integrator circuit according to a second configuration for a second portion of the first time period;
• the second configuration changing polarity of the integrator circuit from the first configuration;
• based on voltage levels at the output terminals of the integrator circuit, generating a clocked output signal representative of a value;
• and
• averaging the value of the clocked output signal over a second time period.

A method of sensing a data state of a memory cell, comprising:

• periodically switching coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, the second configuration changing polarity of the integrator circuit from the first configuration;
• periodically comparing output signals provided by the integrator circuit;
• based on the comparison, generating an output signal having a voltage representative of a value;
• and
• averaging the value of the output signal over a time period.