Split gate memory device and fabricating method thereof

A split gate memory device, comprising:

• a substrate;
• a common source region formed in the substrate;
• drain regions formed in the substrate symmetrically spaced a predetermined distance from the common source region;
• channel regions formed between the common source region and the drain regions;
• a pair of floating gates formed on the substrate on a portion of each of the channel regions and a portion of the source region with a gate insulating layer interposed between the floating gates and the substrate;
• a capping insulating layer formed at a portion of a top surface of each of the floating gates with an inter-gate insulating layer interposed therebetween;
• and
• a pair of control gates formed with a tunnel insulating layer interposed between the control gates and sidewalls of the floating gates and the capping insulating layer.

A method of fabricating a split gate memory device, comprising:

• forming a gate insulating layer and a floating gate layer on a substrate;
• patterning a predetermined region of the floating gate layer to form a floating gate pattern;
• forming a capping insulating layer on portions of the floating gate pattern;
• forming a pair of control gates with a tunnel insulating layer interposed between the control gates and both sidewalls of the floating gate pattern and the capping insulating layer;
• selectively etching the capping insulating layer, the floating gate pattern, and the gate insulating layer until a portion of the substrate is exposed, thereby forming a pair of floating gates;
• forming a common source region by implanting ions into the exposed portion of the substrate;
• and
• forming drain regions by implanting ions into a portion of the substrate adjoining the control gates.

A method of fabricating a split gate memory device, comprising:

• sequentially forming a gate insulating layer and a first polysilicon layer on a substrate;
• forming a polyoxide layer on a predetermined region of the first polysilicon layer;
• patterning the first polysilicon layer using the polyoxide layer as an etching mask;
• forming a capping insulating layer pattern on a portion of the patterned first polysilicon layer having the polyoxide layer;
• forming a tunnel insulating layer and a second polysilicon layer on an entire surface of the substrate including the patterned first polysilicon layer and capping insulating layer;
• anisotropically etching the second polysilicon layer and the tunnel insulating layer to form a pair of control gates that are self-aligned to the second polysilicon layer and the capping insulating layer pattern with the tunnel insulating layer interposed on sidewalls of the patterned first polysilicon layer and capping insulating layer pattern;
• selectively etching the capping insulating layer pattern, the polyoxide layer, the patterned first polysilicon layer and the gate insulating layer until a portion of the substrate is exposed, to form a pair of floating gates;
• implanting ions into the exposed portion of the substrate to form a common source region;
• and
• implanting ions into a portion of the substrate adjoining the control gates to form drain regions.