Integrated circuit memory devices having efficient column select signal generation during normal and refresh modes of operation and methods of operating same

An integrated circuit memory device, comprising:

• an XY array of memory cell sub-blocks, said array comprising first and second offset grids of sub-word line driver control circuits therein, with each of the sub-word line driver control circuits configured to selectively activate a pair of the memory cell sub-blocks in response to an active row select signal and an active column select signal;
• and
• row and column decoder circuitry that is configured drive a selected one of a plurality of row select lines associated with the first grid with an asserted row select signal and is further configured to drive a plurality of column select lines associated with the second grid with asserted column select signals during a write operation.

A method of operating an integrated circuit memory device having an XY array of memory cell sub-blocks therein, comprising the steps of:

• driving a plurality of column select lines that extend across the XY array with asserted column select signals that are received by a plurality of sub-word line driver control circuits in the XY array;
• and
• driving a first row select line that extends across the XY array with an asserted row select signal that is received by at least two of the plurality of sub-word line driver control circuits that are associated with a first row of the XY array during a write operation, while concurrently deasserting a column select signal received by one of the at least two of the plurality of sub-word line driver control circuits.

A method of operating an integrated circuit memory device having an XY array of memory cell sub-blocks therein, comprising the steps of:

• driving a first plurality of column select lines that extend across the XY array with asserted first column select signals that are received by a first plurality of sub-word line driver control circuits in a first row of the XY array, while simultaneously driving a second plurality of column select lines that extend across the XY array with asserted second column select signals that are received by a second plurality of sub-word line driver control circuits in a second row of the XY array;
• and then
• driving a first row select line that is electrically coupled to the first plurality of sub-word line driver control circuits with an asserted row select signal during a write operation, while concurrently deasserting a plurality of the first column select signals.

A method of operating an integrated circuit memory device having an XY array of memory cell sub-blocks therein, comprising the steps of:

• driving a first plurality of column select lines that extend across the XY array with boosted first column select signals that operate to partially activate a first plurality of sub-word line driver control circuits in a first row of the XY array, while simultaneously driving a second plurality of column select lines that extend across the XY array with boosted second column select signals that operate to partially activate a second plurality of sub-word line driver control circuits in a second row of the XY array;
• and then
• driving a first row select line that is electrically coupled to the first plurality of sub-word line driver control circuits with a boosted row select signal, while concurrently deasserting a plurality of the first column select signals and maintaining all of the second column select signals at boosted voltage levels.