Wordline pulldown circuit
AssigneeInfineon Technologies North America Corp.
InventorPaul E. Brucke
Life of this patent
Estimating the term…
Abstract
A circuit and method of operation for pulldown of a wordline in a DRAM (dynamic random access memory) are revealed. The circuit adds a transistor at the far end (top) of each wordline (row) in a DRAM, in addition to a transistor already at the near end (bottom) of each row. An inverter driven by a pulse generator drives the transistors at the top of each wordline, bringing them low in about half the time as a present precharge operation requires.
Claims20
A dynamic random access memory (DRAM) array, comprising:
- a memory array having a plurality of wordlines and bitlines;
- a row decoder connected to each wordline;
- a column decoder connected to each bitline;
- a wordline driver and a pulldown circuit connected to each wordline;
- and
- a pulse generator connected to the pulldown circuits at the end of each wordline, wherein the wordline driver and the pulldown circuit pull down a row of the array upon receiving a signal from the row decoder and the pulse generator.
A dynamic random access memory, comprising:
- at least one memory array, each memory array further comprising a column decoder and a row decoder, wherein each row decoder has a wordline driver for each row;
- a column address buffer and counter connected to the column decoders;
- a row address counter and buffer connected to the row decoders;
- a control logic and timing system connected to the at least one memory array, the column decoders and the row decoders;
- and
- a pulldown circuit connected to the control logic and timing generator, said pulldown circuit connected to an end of each row opposite the wordline driver, wherein the wordline driver and the pulldown circuit pull down a row of the array upon receiving a signal from the control logic and timing generator.
A dynamic random access memory, comprising:
- at least one memory array, each memory array having a plurality of rows and columns, and a row decoder and a column decoder;
- a control logic and timing generator connected to the at least one memory array;
- and
- a pulldown circuit in each memory array, the pulldown circuit connected to each row in the array at an end opposite a connection of the row decoder, wherein the row decoder and the pulldown circuit pull down each row of the array upon receiving a signal from the control logic and timing generator.
A dynamic random access memory, comprising:
- at least one memory array;
- control circuitry for the at least one memory array;
- a row decoder for each said memory array, said row decoder in communication with a wordline driver at a first end of each wordline in the memory array;
- and
- a pulldown circuit in each said memory array, said pulldown circuit in communication with a second end of each wordline in the memory array, wherein the wordline driver and the pulldown circuit pull down a row of the array upon receiving a signal from the control circuitry.
A method of operating a dynamic random access memory (DRAM) array, the method comprising:
- accessing a memory array having a plurality of wordlines and bitlines, and a wordline row decoder connected to a first end of each wordline and having a pulldown circuit connected to a second end of each wordline;
- precharging the array by turning off each row in the wordline, wherein the precharging is accomplished by turning off each row through the row decoder and the pulldown circuit.
A method of pulling down a wordline, the method comprising:
- accessing a wordline with a row decoder at a first end and a pulldown transistor at a second end of the wordline;
- and
- applying a low signal through the row decoder and the pulldown transistor.
A method of operating a dynamic random access memory, the method comprising:
- accessing a memory array having a plurality of wordlines and digitlines, and a wordline row decoder connected to a first end of each wordline and having a pulldown circuit connected to a second end of each wordline;
- precharging the array by turning off each row in the wordline, wherein the precharging is accomplished by turning off each row through the row decoder and the pulldown circuit.
A method of pulling down a wordline, the method comprising:
- accessing a wordline with a row decoder at a first end and a pulldown transistor at a second end of the wordline;
- and
- applying a low signal through the row decoder and the pulldown transistor.
Dependencies are inferred from the claim text.