Clamping Circuit and nonvolatile memory device using the same

A clamping circuit, comprising:

• a first transistor connected between a first node and a second node;
• a charge supply means connected between a gate electrode of the first transistor and a power voltage terminal, for supplying charges to the gate electrode of the first transistor depending on a voltage of the second node in order to control the voltage of the second node;
• a charge discharge means connected between the gate electrode of the first transistor and a ground voltage terminal, for discharging the charges from the gate electrode of the first transistor depending on the voltage of the second node in order to control the second node;
• and
• switching means each connected between a well terminal and a drain terminal of a second transistor constituting the charge discharge means, for applying a bias to the well terminal of the second transistor depending on the gate voltage of the second transistor to lower the threshold voltage of the second transistor.

A clamping circuit, comprising:

• a first transistor connected between a first node and a second node;
• a charge supply means connected between a gate electrode of the first transistor and a power voltage terminal, for supplying charges to the gate electrode of the first transistor depending on a voltage of the second node in order to control the voltage of the second node;
• a charge discharge means connected between the gate electrode of the first transistor and a ground voltage terminal, for discharging the charges from the gate electrode of the first transistor depending on the voltage of the second node in order to control the second node;
• first switching means each connected between a well terminal and a drain terminal of a second transistor constituting the charge supply means, for applying a bias to the well terminal of the second transistor depending on the gate voltage of the second transistor to lower the threshold voltage of the second transistor;
• and
• second switching means each connected between a well terminal and a drain terminal of a third transistor constituting the charge discharge means, for applying a bias to the well terminal of the third transistor depending on the gate voltage of the third transistor to lower the threshold voltage of the third transistor.