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US 2003/0214839 A1Published application
Magnetic random access memory
AssigneeHynix Semiconductor Inc.
InventorsIn Woo Jang, Young Jin Park, Kye Nam Lee, Chang Shuk Kim, Hee Kyung
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Abstract
A magnetic random access memory (MRAM) using a common line is described herein. An MTJ element is positioned on the common line of the MRAM. The common line connected to a source of a transistor transmits a ground level voltage for reading data and supplies a current for writing data.
Claims4
A magnetic random access memory (MRAM) comprising:
- a substrate including a source region, a drain region and a gate region;
- a word line formed on the gate region;
- a source contact formed on the source region;
- a drain contact formed on the drain region;
- a common line electrically connected to the upper portion of the source contact by a first contact plug;
- a metal line electrically connected to the upper portion of the drain contact by a second contact plug;
- a connection film electrically connected to the upper portion of the metal line by a third contact plug, the connection film configured to overlap the upper portion of the common line;
- an MTJ element formed on the connection film and positioned on the common line region;
- and
- a bit line connected to the MTJ element,
- wherein a ground level voltage in a data read operation is applied to the common line, and an amount of current in a data write operation is supplied for the common line.
8 more elements
A magnetic random access memory (MRAM) comprising:
- an MRAM cell including one transistor and one MTJ element connected to a drain of the transistor;
- a bit line connected to the MTJ element;
- a word line connected to a gate of the transistor;
- a common line connected to a source of the transistor;
- first and second transistors connected to both ends of the common line for switching a ground level voltage;
- third and fourth transistors connected in parallel to the first and second transistors at both ends of the common line;
- and
- a current forcing circuit connected individually to the third and fourth transistors, the current forcing circuit configured to supply a current;
- wherein the first and second transistors are turned on to apply the ground level voltage to the common line in a data read operation, and the third and fourth transistors are turned on to supply the current of the current forcing circuit for the common line in a data write operation.
6 more elements
Dependencies are inferred from the claim text.