Silicon controlled rectifier ESD structures with trench isolation

A semiconductor device electrostatic discharge protection structure on a substrate comprising:

• a first doped region of opposite dopent than said substrate extending down from the surface of said substrate;
• a first isolation element at the surface region first lateral boundary between said first doped region and said substrate;
• a heavily doped second region within said first doped region;
• a heavily doped third region within said first doped region;
• a heavily doped fourth region within said substrate of opposite doping than said substrate;
• a heavily doped fifth region within said substrate of similar dopent to said substrate;
• a heavily doped sixth region of same dopent as said doped second region located at the surface region second lateral boundary of said first doped region and said substrate;
• a second isolation element adjacent to said fifth doped region and on opposite side from said fourth doped region;
• a first gate element overlaying the surface region between said second and said third doped regions within said first doped region, and overlaying said surface region between said third doped region and said sixth doped region;
• a second gate element overlying said surface region between said sixth doped region and said forth doped region and said surface region between fourth and fifth doped regions within said substrate;
• a first electrical conduction system connecting said second and third doped regions and said first gate element and to a first voltage source;
• a second electrical conduction system connecting said fourth and fifth doped regions and said second gate element and to a second voltage source;
• a passivation layer overlaying said device surface.

A semiconductor device electrostatic discharge protection structure on a substrate comprising:

• a first doped region of opposite dopent than said substrate extending down from the surface of said substrate;
• a first isolation element at the surface region first lateral boundary between said first doped region and said substrate;
• a heavily doped second region within said first doped region of similar dopent to said first doped region;
• a heavily doped third region within said first doped region of opposite doping than said first doped region;
• a heavily doped fourth region within said substrate of opposite doping than said substrate;
• a heavily doped fifth region within said substrate of similar dopent to said substrate;
• a heavily doped sixth region of same dopent as said doped second region located at the surface region second lateral boundary of said first doped region and said substrate;
• a second isolation element between said forth and sixth heavily doped regions;
• a third isolation element adjacent to said fifth doped region and on opposite side from said fourth doped region;
• a first gate element overlaying the surface region between said second and said third doped regions within said first doped region, and overlaying said surface region between said third and sixth doped regions;
• a second gate element overlying said surface region between said fourth and fifth doped regions within said substrate;
• a first electrical conduction element connecting said second and third doped regions and said first gate element and to a first voltage source;
• a second electrical conduction element connection said fourth and fifth doped regions and said second gate element and to a second voltage source;
• a passivation layer overlaying said device surface.

A method of fabricating a silicon controlled rectifier electrostatic discharge protection device on a semiconductor substrate comprising:

• forming a first insulating layer on the surface of said substrate;
• forming a second insulating layer over said first insulating layer;
• patterning said surface with a masking element for a first doped region within said substrate;
• forming a first doped region on said semiconductor substrate;
• patterning said substrate surface for isolation elements;
• forming said isolation elements;
• planarizing said substrate surface;
• removing first and second insulating layer;
• depositing a third insulating layer;
• forming a first conducting layer upon said third insulating layer;
• patterning said substrate for a plurality of second doped regions;
• forming a plurality of second doped regions within said substrate;
• patterning said substrate for a plurality of third doped regions;
• forming a plurality of third doped regions within said substrate;
• selectively removing said third insulating layer and said first conducting layer;
• forming a forth insulating layer upon said substrate surface;
• forming a conduction system for said protection device;
• forming a passivation layer on said substrate surface.