Clock data recovery circuitry associated with programmable logic device circuitry

A method for recovering clock information from a CDR signal comprising:

• producing a plurality of differently phase-shifted candidate recovered clock signals from a reference clock signal having frequency related to the clock information frequency;
• and
• selecting from the candidate recovered clock signals at least one such signal based on proximity between the phases of that signal and transitions in the CDR signal, the selected candidate recovered clock signal being used as a basis for deriving a recovered clock signal, the selecting being changeable only in response to further transitions in the CDR signal.

Circuitry for recovering clock information from a CDR signal without the CDR signal having to satisfy a run length requirement comprising:

• first circuitry for producing from a reference clock signal, which has frequency having a first predetermined relationship to frequency of the clock information, a plurality of candidate recovered clock signals, all of the candidate recovered clock signals having frequency that has a second predetermined relationship to the frequency of the clock information, and the candidate recovered clock signals having respective different phases that subdivide a cycle of the clock information;
• and
• second circuitry for selecting at least one of the candidate recovered signals for use as a basis for a recovered clock signal based on proximity of transitions in the CDR signal to transitions in the selected candidate recovered clock signal, the second circuitry maintaining a selection it has made until subsequent transitions in the CDR signal have closer proximity to transitions in another of the candidate recovered clock signals.