Memory circuit testing system, semiconductor device, and memory testing method

A semiconductor device including:

• a plurality of memory circuits;
• and
• a plurality of testing circuits corresponding to the plurality of memory circuits, each testing circuit sequentially executing a first testing state for writing data to the corresponding memory circuit, a second testing state for waiting until a release signal is input, and a third testing state for reading data from each memory circuit;
• the semiconductor device being characterized in that, wherein the second testing state includes a refresh means for performing a refresh operation on the corresponding memory circuit until the first testing state ends for all of the plurality of testing circuits.

A memory testing method for testing a plurality of memory circuits with a plurality testing circuits corresponding testing circuits, the method comprising sequentially executing with each of the testing circuits:

• a first testing state with each of the testing circuits for writing data to the corresponding memory circuit;
• a second testing state for waiting until a release signal is input after a refresh operation has been performed for each corresponding memory circuit until the first testing state has ends for all of the testing circuits;
• and
• a third testing state for reading data from each memory circuit.