Method for high-speed data transfer across LDT and PCI buses

A multiple processor system, comprising:

• a first chip;
• and
• a second chip:
• wherein a first substantially write-only communication link is established from said first chip to said second chip using a write-only message-based link protocol.

A method for establishing a write-only communication link from a first chip to a second chip using a link driver wherein each chip comprising a means to transfer memory, a means to generate interrupt, a means to keep track of said link, and a means to receive requests, said method comprising the steps of:

• said first chip sending a start command to notify said second chip that said first driver is starting;
• said first chip sending an init command to said second chip to synchronize said communication link;
• said second chip receiving said init command from said first chip;
• said second chip sending a start command to synchronize said communication link;
• and
• said means to transfer memory sending a run command to start data transferring across said communication link.

A computer readable storage medium containing a computer readable code for operating a computer system to implement a method for establishing a write-only communication link from a first chip to a second chip using a link driver wherein each chip comprising a means to transfer memory, a means to generate interrupt, a means to keep track of state of said write-only communication link, and a means to receive requests, said method comprising the steps of:

• said first chip sending a start command to notify said second chip that said first driver is starting;
• said first chip sending an init command to said second chip to synchronize said communication link;
• said second chip receiving said init command from said first chip;
• said second chip sending a start command to synchronize said communication link;
• and
• said means to transfer memory sending a run command to start data transferring across said communication link.