Graded/stepped silicide process to improve mos transistor
AssigneeSTMicroelectronics S.r.l.
InventorsFuchao Wang, Ming Fang
Life of this patent
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Abstract
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.
Claims14
A method of forming a portion of an integrated circuit, comprising:
- forming a first silicide region over a device structure within the integrated circuit, the first silicide region having a first silicon/metal ratio;
- and
- forming a second silicide region on the first silicide region, the second silicide region having a second silicon/metal ratio greater than the first silicon/metal ratio.
A portion of an integrated circuit, comprising:
- a polysilicon conductive structure;
- a silicide on the polysilicon conductive structure;
- and
- an oxide on the silicide,
- wherein the silicide has higher stochiometric ratios of silicon to metal at interfaces between the silicide and the polysilicon conductive structure and between the silicide and the oxide than within an inner region of the silicide.
A method of forming a portion of an integrated circuit, comprising:
- forming a polysilicon conductive structure;
- forming a silicide on the polysilicon conductive structure;
- and
- forming an oxide on the silicide,
- wherein the silicide has higher stochiometric ratios of silicon to metal at interfaces between the silicide and the polysilicon conductive structure and between the silicide and the oxide than within an inner region of the silicide.
A portion of an integrated circuit, comprising:
- a first silicide region over a device structure within the integrated circuit, the first silicide region having a first silicon/metal ratio;
- and
- a second silicide region on the first silicide region, the second silicide region having a second silicon/metal ratio greater than the first silicon/metal ratio.
Dependencies are inferred from the claim text.