Metal sandwich structure for MIM capacitor onto dual damascene

A method of forming conductive interconnect plugs and interconnect plugs to a Metal-Insulator-Metal capacitor by applying the dual damascene process, comprising the steps of:

• providing a substrate, said substrate having been provided with semiconductor devices in or over the surface thereof;
• providing a first level of dual damascene interconnect plugs through a first layer of dielectric deposited over the surface of said substrate, said first level of dual damascene interconnect plugs comprising at least one first and at least one second dual damascene interconnect plug;
• creating at least one Metal-Insulator-Metal capacitor over the surface of said first layer of dielectric aligned with said at least one first dual damascene interconnect plug;
• depositing a layer of etch stop material over the surface of said first layer of dielectric, thereby including exposed surfaces of said at least one Metal-Insulator-Metal capacitor;
• providing a second level of dual damascene interconnect plugs through a second layer of dielectric deposited over the surface of said first layer of dielectric and through said layer of etch stop material, said second level of dual damascene interconnect plugs comprising at least one third and at least one fourth dual damascene interconnect plug, said at least one third dual damascene interconnect plug being aligned with said at least one Metal-Insulator-Metal capacitor, said at least one fourth dual damascene interconnect plug being aligned with said at least one second dual damascene interconnect plug;
• and
• depositing a layer of passivation material over the surface of said second layer of dielectric.

A method of forming conductive interconnect plugs and interconnect plugs to a Metal-Insulator-Metal capacitor by applying the dual damascene process, comprising the steps of:

• providing a substrate, said substrate having been provided with semiconductor devices in or over the surface thereof;
• depositing a first layer of dielectric over the surface of said substrate;
• patterning and etching said first layer of dielectric, creating at least one first dual damascene opening and at least one second dual damascene opening through said first layer of dielectric;
• filling said at least one first and said at least one second dual damascene opening with a metal, creating at least one first and at least one second dual damascene plug;
• creating at least one Metal-Insulator-Metal capacitor over the surface of said first layer of dielectric, said at least one Metal-Insulator-Metal capacitor being aligned with said least one first dual damascene opening;
• depositing a layer of etch stop material over the surface of said first layer of dielectric, thereby including exposed surfaces of said at least one Metal-Insulator-Metal capacitor;
• depositing a second layer of dielectric over the surface of said layer of etch stop material;
• patterning and etching said second layer of dielectric, creating at least one third dual damascene opening and at least one fourth dual damascene opening through said second layer of dielectric and said layer of etch stop material, said at least one third opening being aligned with said at least one Metal-Insulator-Metal capacitor, said at least one fourth opening being aligned with said at least one second opening created through said first layer of dielectric;
• and
• filling said at least one third and said at least one fourth dual damascene opening with a metal, creating at least one third and at least one fourth dual damascene plug.

A method of forming conductive interconnect plugs and interconnect plugs to a Metal-Insulator-Metal capacitor by applying the dual damascene process, comprising the steps of:

• providing a substrate, said substrate having been provided with semiconductor devices in or over the surface thereof;
• depositing a first layer of dielectric over the surface of said substrate;
• patterning and etching said first layer of dielectric, creating at least one first dual damascene opening and at least one second dual damascene opening through said first layer of dielectric;
• filling said at least one first and said at least one second dual damascene opening with copper, creating at least one first and at least one second copper dual damascene plug;
• creating at least one Metal-Insulator-Metal capacitor over the surface of said first layer of dielectric, said at least one Metal-Insulator-Metal capacitor being aligned with said least one first dual damascene opening;
• depositing a layer of etch stop material over the surface of said first layer of dielectric, thereby including exposed surfaces of said at least one Metal-Insulator-Metal capacitor;
• depositing a second layer of dielectric over the surface of said layer of etch stop material;
• patterning and etching said second layer of dielectric, creating at least one third dual damascene opening and at least one fourth dual damascene opening through said second layer of dielectric and said layer of etch stop material, said at least one third opening being aligned with said at least one Metal-Insulator-Metal capacitor, said at least one fourth opening being aligned with said at least one second opening created through said first layer of dielectric;
• and
• filling said at least one third and said at least one fourth dual damascene opening with copper, creating at least one third and at least one fourth copper dual damascene plug.

A method of forming conductive interconnect plugs and interconnect plugs to a Metal-Insulator-Metal capacitor by applying the dual damascene process, comprising the steps of:

• providing a substrate, said substrate having been provided with semiconductor devices in or over the surface thereof;
• depositing a first layer of dielectric over the surface of said substrate;
• patterning and etching said first layer of dielectric, creating at least one first dual damascene opening and at least one second dual damascene opening through said first layer of dielectric;
• filling said at least one first and said at least one second dual damascene opening with copper, creating at least one first and at least one second copper dual damascene plug;
• creating at least one Metal-Insulator-Metal capacitor over the surface of said first layer of dielectric, said at least one Metal-Insulator-Metal capacitor being aligned with said least one first dual damascene opening, said creating at least one Metal-Insulator-Metal capacitor comprising the steps of:
• (i) depositing a first layer of capacitor electrode material over the surface of said first layer of dielectric;
• then
• (ii) depositing a layer of capacitor dielectric material over the surface of said first layer of capacitor electrode material;
• then
• (iii) depositing a second layer of capacitor electrode material over the surface of said layer of capacitor dielectric material;
• and then
• (iv) patterning and etching by applying a one-step etch said second layer of capacitor electrode material, said layer of capacitor dielectric material and said first layer of capacitor electrode material;
• depositing a layer of etch stop material over the surface of said first layer of dielectric, thereby including exposed surfaces of said at least one Metal-Insulator-Metal capacitor;
• depositing a second layer of dielectric over the surface of said layer of etch stop material;
• patterning and etching said second layer of dielectric, creating at least one third dual damascene opening and at least one fourth dual damascene opening through said second layer of dielectric and said layer of etch stop material, said at least one third opening being aligned with said at least one Metal-Insulator-Metal capacitor, said at least one fourth opening being aligned with said at least one second opening created through said first layer of dielectric;
• and
• filling said at least one third and said at least one fourth dual damascene opening with copper, creating at least one third and at least one fourth copper dual damascene plug.

A method of forming conductive interconnect plugs and interconnect plugs to a Metal-Insulator-Metal capacitor by applying the dual damascene process, comprising the steps of:

• providing a substrate, said substrate having been provided with semiconductor devices in or over the surface thereof;
• depositing a first layer of dielectric over the surface of said substrate;
• patterning and etching said first layer of dielectric, creating at least one first dual damascene opening and at least one second dual damascene opening through said first layer of dielectric;
• filling said at least one first and said at least one second dual damascene opening with copper, creating at least one first and at least one second copper dual damascene plug;
• creating at least one Metal-Insulator-Metal capacitor over the surface of said first layer of dielectric, said at least one Metal-Insulator-Metal capacitor being aligned with said least one first dual damascene opening, said creating at least one Metal-Insulator-Metal capacitor comprising the steps of:
• (i) depositing a first layer tantalum over the surface of said first layer of dielectric;
• then
• (ii) depositing a first layer of silicon nitride over the surface of said first layer of capacitor electrode material;
• then
• (iii) depositing a second layer of tantalum over the surface of said layer of capacitor dielectric material;
• and then
• (iv) patterning and etching by applying a one-step etch said second layer of tantalum, said first layer of silicon nitride and said first layer of tantalum;
• depositing a second layer of silicon nitride over the surface of said first layer of dielectric, thereby including exposed surfaces of said at least one Metal-Insulator-Metal capacitor;
• depositing a second layer of dielectric over the surface of said layer of etch stop material;
• patterning and etching said second layer of dielectric, creating at least one third dual damascene opening and at least one fourth dual damascene opening through said second layer of dielectric and said second layer of silicon nitride, said at least one third opening being aligned with said at least one Metal-Insulator-Metal capacitor, said at least one fourth opening being aligned with said at least one second opening created through said first layer of dielectric;
• and
• filling said at least one third and said at least one fourth dual damascene opening with copper, creating at least one third and at least one fourth copper dual damascene plug.