Method of fabricating trap type nonvolatile memory device

Abstract

A method of forming a trap type nonvolatile memory device is disclosed. The method includes forming a cell gate insulating layer on a semiconductor substrate. The semiconductor substrate includes a peripheral circuit region and a cell array region. A sacrificial pattern is formed on the cell gate insulating layer to cover the cell array region. The cell gate insulating layer in the peripheral circuit region is then etched using the sacrificial pattern as an etch mask to expose the semiconductor substrate in the peripheral circuit region. The cell gate insulating layer includes a lower insulating layer, a charge storage layer, and an upper insulating layer. Also, the upper insulating layer and the sacrificial pattern are made of material layers having an etch selectivity with respect to each other. The upper insulating layer is made of a metal oxide layer having an etch selectivity with respect to the sacrificial pattern.

Dependencies are inferred from the claim text.