US 2003/0211689 A1 · Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same

Abstract

A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked. A lower insulating pattern, which is covered with the charge storage layer and thicker than the tunnel insulating pattern, is disposed on the semiconductor substrate beside the tunnel insulating layer. A heavily doped region including impurities of the same type as the semiconductor substrate is disposed in the semiconductor substrate under the tunnel insulating pattern.

Claims19

Dependent claims

A non-volatile memory device comprising:

a semiconductor substrate of a first conductivity type;
a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked on the semiconductor substrate;
a lower insulating pattern and a tunnel insulating pattern interposed between the charge storage layer and the semiconductor substrate;
and
a heavily doped region of the first conductivity type formed in the semiconductor substrate under the tunnel insulating pattern, wherein the tunnel insulating pattern is thinner than the lower insulating pattern in thickness and disposed at the side of the lower insulating pattern.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/420,237Filed 22 Apr 2003

Priority

KR 2002-250127 May 2002

Published

13 Nov 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 30/0217
Of FETs having insulated gates [IGFET]: forming self-aligned punch-through stoppers or threshold implants under gate regions

Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same

Life of this patent

Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same

Life of this patent

Abstract

Claims19