Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

A method of forming a sub-0.05 μm channel length fully-depleted SOI MOSFET device comprising the steps of:

• forming at least one dummy gate region atop an SOI layer, said dummy gate region comprising at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of said sacrificial polysilicon region;
• forming an oxide layer that is coplanar with an upper surface of said dummy gate region;
• removing said sacrificial polysilicon region to expose a portion of the SOI layer;
• forming a thinned device channel region in said exposed portion of the SOI layer;
• forming inner nitride spacers on exposed walls of said first nitride spacers;
• forming a gate region over said thinned device channel region;
• and
• removing said oxide layer so as to expose thicker portions of said SOI layer than said device channel region.