Flip chip interface circuit of a semiconductor memory device and method for interfacing a flip chip

A flip chip interface circuit of a semiconductor memory device for interfacing with a flip chip package,

• the flip chip package having:
• a first semiconductor chip provided on an upper side of an assembling lead frame having first and second address pads, first and second bonding option pads, and various pads formed thereon;
• and
• a second semiconductor chip provided under the assembling lead frame wherein the first and second address pads, first and second bonding option pads, and various pads that are formed on the first semiconductor chip are also symmetrically arranged on the second semiconductor chip in a mirror type arrangement relative to the first semiconductor chip,
• wherein the first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips, the first bonding option pad of the first semiconductor chip is connected to Vcc, the second bonding option pad of the first semiconductor chip is not connected to ground nor electrically connected, the second bonding option pad of the second semiconductor chip is connected to Vcc, and the first bonding option pad of the second semiconductor chip is not connected to ground nor electrically connected,
• the flip chip interface circuit comprising:
• a chip selection circuit for outputting first and second input pad selection signals and first and second semiconductor chip selection signals in response to signals input from the first and second address pads and the first and second bonding option pads;
• a control circuit for controlling input/output of the first and second semiconductor chips in response to inputs of the first and second semiconductor chip selection signals and the first and second input pad selection signals output from the chip selection circuit;
• and
• an input circuit for transmitting data input from a plurality of pads formed in the first and second semiconductor chips to the first and second semiconductor chips in response to first and second semiconductor chip selection input control signals of the control circuit.

A flip chip interfacing method for a semiconductor memory device having a packaged flip chip,

• the packaged flip chip having:
• a first semiconductor chip provided on an upper surface of an assembling lead frame in a flip chip package in which two identical chips are bonded, the first semiconductor chip having at least first and second address pads and first and second bonding option pads formed thereon;
• and
• a second semiconductor chip provided under the assembling lead frame, wherein the at least first and second address pads and first and second bonding option pads formed on the first semiconductor chip are also symmetrically formed on the second semiconductor chip in a mirror type arrangement to the first semiconductor chip,
• wherein the first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips, the first bonding option pad of the first semiconductor chip is connected to Vcc, the second bonding option pad of the first semiconductor chip is not connected to ground nor electrically connected, the second bonding option pad of the second semiconductor chip is connected to Vcc, and the first bonding option pad of the second semiconductor chip is not connected to ground nor electrically connected,
• the flip chip interfacing method comprising:
• outputting the first and second input pad selection signals and the chip selection signals in response to signals input from the first and second address pads and the first and second bonding option pads of the first and second semiconductor chips;
• outputting the first and second semiconductor chip selection signals by using the first and second input pad selection signals and the chip selection signals;
• and
• outputting an interface enable signal for controlling data input/output of the first and second semiconductor chips in response to the first and second semiconductor chip selection signals.