Configurable packet processor

A method for packet processing in a packet processing system, the method comprising:

• a step for obtaining first information regarding a packet;
• a step for retrieving an entry corresponding to the first information from a parser memory;
• a step for retrieving from the packet one or more protocol bits identified by the parser memory entry;
• a step for retrieving from a match engine memory a match engine memory entry comprising an action to perform using a match engine key comprising a combination of the protocol bits and a match engine index;
• and,
• a step for performing the action specified in the retrieved match engine entry.

A packet processing apparatus comprising:

• a control logic circuit;
• a parser memory accessible to the control logic circuit the parser memory comprising a plurality of entries each specifying a location in a packet of one or more protocol bits and at least some of which specifying a match engine index;
• a match engine memory accessible to the control logic circuit, the match engine memory comprising a plurality of entries each specifying an action to be taken;
• and,
• a context memory accessible to the control logic circuit, the context memory comprising a plurality of entries each specifying a match engine index;
• wherein the control logic circuit is configured to generate a match engine key by combining protocol bits of a packet identified in a parser memory entry with a match engine index from an entry of either the parser memory or the context memory, to retrieve from the match engine memory an entry corresponding to the match engine key, and to perform an action specified in the match engine entry.

A configurable device for processing packets, the device supporting a plurality of protocols, the device comprising:

• a first internal memory comprising a plurality of entries;
• a second internal memory comprising a plurality of entries each comprising an action to be taken on the packet;
• logic circuitry for identifying a channel value associated with the packet, retrieving an entry from the first memory using the channel value as an index, and obtaining from the entry address information identifying a set of entries in an external context memory applicable to the channel value;
• logic circuitry for using the address information and one or more bit values from the packet to retrieve from the external context memory one entry from the set of entries;
• and,
• logic circuitry for using information from the one entry retrieved from the external context memory to retrieve from the second memory an action to be taken on the packet.

A packet processing device comprising:

• means for retrieving first information about a received packet;
• means for retrieving an entry corresponding to the first information, the entry comprising a location in the packet of one or more protocol bits specifying a protocol associated with the packet and a match engine index;
• means for generating a match engine key;
• and,
• means for retrieving an action corresponding to one of a plurality of match engine entries which matches the match engine key;
• and,
• means for performing the action.

A method for processing packets in which a plurality of protocols are supported, comprising the steps of:

• providing in a processing device, first and second internal memories;
• obtaining from said first internal memory, based on a channel on which said packet is received, address information to access an external memory containing context information associated with said packet;
• and
• obtaining from said second internal memory, based on matching label and index information obtained from said external memory, an action to be executed with respect to said packet.

A device for processing packets in which a plurality of protocols are supported, the device comprising:

• first and second internal memories wherein;
• said first internal memory provides, based on a channel on which said packet is received, address information to access an external memory containing context information associated with said packet;
• and
• said second internal memory provides, based on matching label and index information obtained from said external memory, an action to be executed with respect to said packet.