Semiconductor memory device with mode register and method for controlling deep power down mode therein

A semiconductor memory device with a mode register, the semiconductor memory device comprising:

• a deep power down decoder for receiving external clock, clock enable, and command signals and for generating an intermediate deep power down mode entry signal instructing the semiconductor memory device to enter into a deep power down mode in response to a predetermined combination of the received external clock, clock enable, and command signals;
• a mode register setting decoder for receiving the external clock and command signals, and for generating a mode register setting signal instructing a setting of the mode register in response to a predetermined combination of the received external clock and command signals;
• a mode register setting latch circuit for latching the mode register setting signal from the mode register when the mode register setting signal is received after stabilization of an external power supply;
• and
• a deep power down mode controller for receiving the intermediate deep power down mode entry signal from the deep power down decoder, and for generating a final deep power down mode entry signal when the mode register setting signal is received from the command decoder.

A method for controlling a deep power down mode in a semiconductor memory device with a mode register, the method comprising the steps of:

• (i) receiving external clock, clock enable, and command signals, and generating an intermediate deep power down mode entry signal instructing the semiconductor memory device to enter into a deep power down mode or a mode register setting signal commanding a setting of the mode register according to a predetermined combination of the received internal clock, clock enable, and external command signals;
• (ii) latching the mode register setting signal when the mode register setting signal is received after a stabilization of the external power supply voltage;
• and
• (iii) generating a final deep power down mode entry signal when the intermediate deep power down entry and mode register setting signals are received.