Low-voltage semiconductor memory device

A device comprising:

• a memory cell array, wherein the memory cell array comprises a plurality of word lines, a plurality of bit lines and a plurality of memory cells, wherein the plurality of memory cells are arranged according to a matrix formed by the plurality of word lines and the plurality of bit lines, and wherein the plurality of bit lines are divided into a plurality of input/output groups;
• a row selection circuit for selecting at least one of the word lines in response to a row address signal;
• a column selection circuit that selects at least one of the bit lines from every one of the plurality of input/output groups in response to a column address signal;
• an amplification circuit that detects a voltage change on the at least one of the bit lines selected by the column selection circuit;
• a discharge control circuit that generates discharge signals corresponding to the plurality of bit lines in response to a transition of the row address signal and the column address signal;
• and
• a discharge circuit that selectively discharges the voltages of the plurality of bit lines in response to the discharge signals, the discharge circuit further comprising a plurality of bit-line discharge units each corresponding to a respective one of the plurality of input/output groups, each of the bit-line discharge units having a first transistor and a second transistor coupled in series between a corresponding one of the plurality of bit lines and a ground voltage, a gate of the first transistor being coupled to a voltage higher than a power supply voltage, and a gate of the second transistor receiving a corresponding one of the discharge signals.

A device comprising:

• a memory cell array divided into a plurality of memory blocks, wherein each of the memory blocks comprises a plurality of word lines, a plurality of local bit lines and a plurality of memory cells, wherein the plurality of memory cells are arranged according to a matrix formed by the plurality of word lines and the plurality of local bit lines, wherein the plurality of local bit lines are grouped into a plurality of segments;
• a plurality of global bit lines each corresponding to one of the plurality of segments, wherein the plurality of global bit lines is grouped into a plurality of input/output groups;
• a plurality of first column selection circuits each corresponding to one of the plurality of memory blocks that selects at least one of the plurality of local bit lines from the plurality of segments;
• a second column selection circuit that selects any one of the plurality of global bit lines from the plurality of input/output groups and couples the selected any one of the plurality of global bit lines to a data line, wherein the data line corresponds to the input/output group containing the selected any one of the plurality of global bit lines;
• a discharge control circuit that generates discharge signals in response to a transition of a row address signal and a transition of a column selection signal;
• and
• a discharge circuit that selectively discharges the voltages of the plurality of global bit lines in response to the discharge signals, the discharge circuit further comprising a plurality of bit-line discharge units each corresponding to one of the plurality of input/output groups, wherein each of the bit-line discharge units has a first transistor and a second transistor coupled in series between a corresponding one of the plurality of global bit lines and a ground voltage, wherein a gate of the first transistor is coupled to a voltage higher than a power supply voltage, and wherein a gate of the second transistor receiving a corresponding one of the discharge signals.