US 2003/0210576 A1 · Programmable memory devices with latching buffer circuit and methods for operating the same

Abstract

Programmable memory devices include a memory cell having an associated bit line. A buffer circuit couples the bit line to a data line. The buffer circuit has a sense node coupled to the bit line and includes a latch circuit having a latch node coupled to the data line. A control circuit resets the latch node between a program operation of the memory cell and its corresponding program-verify operation. The memory devices may be NAND-type flash memory devices and the memory cell may be one of a string of memory cells connected in series between the bit line and a common source line. A transistor may couple the data line to the latch node and a transistor may couple the latch node to the sense node. Methods of operating the same are also provided.

Claims28

Dependent claims

A programmable memory device comprising:

a memory cell having an associated bit line;
a buffer circuit that couples the bit line to a data line, the buffer circuit having a sense node coupled to the bit line and including a latch circuit having a latch node coupled to the data line;
and
a control circuit that resets the latch node between a program operation of the memory cell and its corresponding program-verify operation.

1 more element

A semiconductor memory device comprising:

a memory cell array having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells arranged in a matrix of the word lines and the bit lines;
a page buffer group having a plurality of page buffers and connected to the bit lines of the memory cell array;
and
a column-pass gate circuit connected between the page buffer group and a data bus,
wherein each of the page buffers includes:
a first transistor having a drain connected to a first node, a source, and a gate connected to receive a first control signal;
a first latch having a first latch node connected to the source of the first transistor and a second latch node;
a second transistor having a drain connected to a sensing node, a source connected to the first node, and a gate connected to receive a second control signal;
a second latch having a third latch node connected to the source of the second transistor and the first node, and a fourth latch node;
a third transistor having a drain connected to the fourth latch node, a source, and a gate connected to the sensing node;
a fourth transistor having a drain connected to the fourth latch node, a source, and a gate connected to the first latch node;
and
a fifth transistor having a drain connected to the sources of the third and fourth transistors, a source grounded, and a gate connected to receive a third control signal.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/403,739Filed 31 Mar 2003

Priority

KR 2002-002625913 May 2002

Published

13 Nov 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 16/3459
Arrangements for verifying correct programming or for detecting overprogrammed cells: circuits or methods to verify correct programming of…
G11C 7/065
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of latching type
G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits
G11C
Static stores

Programmable memory devices with latching buffer circuit and methods for operating the same

Life of this patent

Programmable memory devices with latching buffer circuit and methods for operating the same

Life of this patent

Abstract

Claims28