Device including a resistive path to introduce an equivalent RC circuit

A device comprising:

• a bulk material of a P-type conductivity;
• source and drain regions positioned within said bulk material and separated by a channel region, said source and drain regions having an N-type conductivity;
• a gate positioned over said channel region;
• and
• a resistive path in said bulk material, said resistive path being positioned in said bulk material so as to couple a first location in said bulk material, below said channel region, to a second location in said bulk material, said resistive path having a horizontal length, wherein;
• said horizontal length of said resistive path is chosen to provide a resistance between said first location and said second location within a specific range of resistance values.

A device comprising:

• a bulk material of a N-type conductivity;
• source and drain regions positioned within said bulk material and separated by a channel region, said source and drain regions having a P-type conductivity;
• a gate positioned over said channel region;
• and
• a resistive path in said bulk material, said resistive path being positioned in said bulk material so as to couple a first location in said bulk material, below said channel region, to a second location in said bulk material, said resistive path having a horizontal length, wherein;
• said horizontal length of said resistive path is chosen to provide a resistance between said first location and said second location within a specific range of resistance values.

A device comprising:

• a bulk material of a first conductivity type;
• source and drain regions positioned within said bulk material and separated by a channel region, said source and drain regions having a second conductivity type, said source being coupled to a second supply voltage;
• a gate positioned over said channel region;
• a resistive path in said bulk material, said resistive path being positioned in said bulk material so as to couple a first location in said bulk material, below said channel region, to a second location in said bulk material, said resistive path having a horizontal length;
• and
• a well tie of said first conductivity type positioned within said bulk material, said well tie being positioned beside one of said source or drain regions and outside said channel region, said well tie being electrically coupled to said second location in said bulk material, said well tie being coupled to a first supply voltage, wherein;
• said horizontal length of said resistive path is chosen to provide a resistance between said first location and said second location within a specific range of resistance values, further wherein;
• said device is characterized as having an on current and an off current and the ratio of on current to off current in said device is not greater than about 105, further wherein;
• said device has an unbiased threshold voltage of between about −150 millivolts and +150 millivolts.

A device comprising:

• a substrate having a first dopant concentration of a first conductivity type;
• an epitaxial layer formed on said substrate, said epitaxial layer having a second dopant concentration of said first conductivity type;
• source and drain regions positioned within said epitaxial layer and separated by a channel region, said source and drain regions having a second conductivity type;
• a gate positioned over said channel region;
• and
• a resistive path, said resistive path being positioned in said epitaxial layer and said substrate so as to couple a first location in said epitaxial layer, below said channel region, to a second location in said epitaxial layer, said resistive path having a horizontal length in said substrate, wherein;
• said horizontal length of said resistive path is chosen to provide a resistance between said first location and said second location in said epitaxial layer within a specific range of resistance values.

A device comprising:

• a substrate having a first dopant concentration of a first conductivity type;
• an epitaxial layer formed on said substrate, said epitaxial layer having a second dopant concentration of said first conductivity type;
• source and drain regions positioned within said epitaxial layer and separated by a channel region, said source and drain regions having a second conductivity type;
• a gate positioned over said channel region;
• a resistive path, said resistive path being positioned in said epitaxial layer and said substrate so as to couple a first location in said epitaxial layer, below said channel region, to a second location in said epitaxial layer, said resistive path having a horizontal length in said substrate;
• and
• a well tie of said first conductivity type positioned within said bulk material, said well tie being positioned beside one of said source or drain regions and outside said channel region, said well tie being electrically coupled to said second location in said bulk material, said well tie being coupled to a first supply voltage, wherein;
• said horizontal length of said resistive path is chosen to provide a resistance between said first location and said second location in said epitaxial layer within a specific range of resistance values, further wherein;
• said device is characterized as having an on current and an off current and the ratio of on current to off current in said device is not greater than about 105, further wherein;
• said device has an unbiased threshold voltage of between about −150 millivolts and +150 millivolts.

A device comprising:

• a substrate of a first conductivity type;
• a surface well having a first dopant concentration of a second conductivity type formed in said substrate;
• source and drain regions positioned within said surface well and separated by a channel region, said source and drain regions having said first conductivity type;
• a gate positioned over said channel region;
• a buried well having a second dopant concentration of said second conductivity type, said buried well being positioned in said substrate, below said surface well;
• and
• a resistive path, said resistive path being positioned so as to couple a first location in said surface well, below said channel region, to a second location in said surface well, said resistive path having a horizontal length in said buried well, wherein;
• said horizontal length of said resistive path in said buried well is chosen to provide a resistance between said first location and said second location in said surface well within a specific range of resistance values.

A device comprising:

• a substrate of a first conductivity type;
• a surface well having a first dopant concentration of a second conductivity type formed in said substrate;
• source and drain regions positioned within said surface well and separated by a channel region, said source and drain regions having said first conductivity type;
• a gate positioned over said channel region;
• a buried well having a second dopant concentration of said second conductivity type, said buried well being positioned in said substrate, below said surface well;
• a resistive path, said resistive path being positioned so as to couple a first location in said surface well, below said channel region, to a second location in said surface well, said resistive path having a horizontal length in said buried well;
• and
• a well tie of said first conductivity type positioned within said surface well, said well tie being positioned beside one of said source or drain regions and outside said channel region, said well tie being electrically coupled to said second location in said surface well, said well tie being coupled to a first supply voltage, wherein;
• said horizontal length of said resistive path in said buried well is chosen to provide a resistance between said first location and said second location in said surface well within a specific range of resistance values, further wherein;
• said device is characterized as having an on current and an off current and the ratio of on current to off current in said device is not greater than about 105, further wherein;
• said device has a threshold voltage of between about −150 millivolts and +150 millivolts.

A device comprising:

• a substrate having a first dopant concentration of a first conductivity type;
• a layer formed on said substrate, said layer having a second dopant concentration of said first conductivity type;
• source and drain regions positioned within said layer and separated by a channel region, said source and drain regions having a second conductivity type;
• a gate positioned over said channel region;
• a buried well having a second dopant concentration of said second conductivity type, said buried well being positioned between said substrate and said layer, said buried well having a perforation;
• and
• a resistive path, said resistive path being positioned in said layer and said substrate so as to couple a first location in said layer, below said channel region, to a second location in said layer, said resistive path having a horizontal length in said substrate that is coupled to said first and second locations in said layer through said perforation in said buried well, wherein;
• said horizontal length of said resistive path in said substrate is chosen to provide a resistance between said first location and said second location in said layer within a specific range of resistance values.

A device comprising:

• a substrate having a first dopant concentration of a first conductivity type;
• a layer formed on said substrate, said layer having a second dopant concentration of said first conductivity type;
• source and drain regions positioned within said layer and separated by a channel region, said source and drain regions having a second conductivity type, said source being coupled to a second supply voltage;
• a gate positioned over said channel region;
• a buried well having a second dopant concentration of said second conductivity type, said buried well being positioned between said substrate and said layer, said buried well having a perforation;
• a well tie of said first conductivity type positioned within said layer, said well tie being positioned beside one of said source or drain regions and outside said channel region, said well tie being electrically coupled to said second location in said layer, said well tie being coupled to a first supply voltage;
• and
• a resistive path, said resistive path being positioned in said layer and said substrate so as to couple a first location in said layer, below said channel region, to a second location in said layer, said resistive path having a horizontal length in said substrate that is coupled to said first and second locations in said layer through said perforation in said buried well, wherein;
• said horizontal length of said resistive path in said substrate is chosen to provide a resistance between said first location and said second location in said layer within a specific range of resistance values, further wherein;
• said device is characterized as having an on current and an off current and the ratio of on current to off current in said device is not greater than about 105, further wherein;
• said device has an unbiased threshold voltage of between about −150 millivolts and +150 millivolts.

A structure comprising:

• a substrate having a first dopant concentration of a first conductivity type;
• a layer formed on said substrate, said layer having a second dopant concentration of said first conductivity type;
• a surface well having a first dopant concentration of a second conductivity type formed in said layer;
• a first transistor having source and drain regions positioned within said layer and separated by a channel region, said source and drain regions having a second conductivity type, and a gate positioned over said channel region;
• a second transistor having source and drain regions positioned within said surface well and separated by a channel region, said source and drain regions having said first conductivity type, and a gate positioned over said channel region;
• a buried well having a second dopant concentration of said second conductivity type, said buried well being positioned between said substrate and said layer, said buried well having a perforation;
• a first resistive path, said first resistive path being positioned in said layer and said substrate so as to couple a first location in said layer, below said channel region of said first transistor, to a second location in said layer, said first resistive path having a horizontal length in said substrate that is coupled to said first and second locations in said layer through said perforation in said buried well, wherein;
• said horizontal length of said first resistive path in said substrate is chosen to provide a resistance between said first location and said second location in said layer within a specific range of resistance values;
• and
• a second resistive path, said second resistive path being positioned so as to couple a first location in said surface well, below said channel region of said second transistor, to a second location in said surface well, said second resistive path having a horizontal length in said buried-well, wherein;
• said horizontal length of said second resistive path in said buried well is chosen to provide a resistance between said first location and said second location in said surface well within a specific range of resistance values.

A structure comprising:

• a substrate having a first dopant concentration of a first conductivity type;
• a layer formed on said substrate, said layer having a second dopant concentration of said first conductivity type;
• a surface well having a first dopant concentration of a second conductivity type formed in said layer;
• a first transistor having source and drain regions positioned within said layer and separated by a channel region, said source and drain regions having a second conductivity type, and a gate positioned over said channel region;
• a second transistor having source and drain regions positioned within said surface well and separated by a channel region, said source and drain regions having said first conductivity type, and a gate positioned over said channel region;
• a buried well having a second dopant concentration of said second conductivity type, said buried well being positioned between said substrate and said layer, said buried well having a perforation;
• a first resistive path, said first resistive path being positioned in said layer and said substrate so as to couple a first location in said layer, below said channel region of said first transistor, to a second location in said layer, said first resistive path having a horizontal length in said substrate that is coupled to said first and second locations in said layer through said perforation in said buried well, wherein;
• said horizontal length of said first resistive path in said substrate is chosen to provide a resistance between said first location and said second location in said layer within a specific range of resistance values;
• and
• a second resistive path, said second resistive path being positioned so as to couple a first location in said surface well, below said channel region of said second transistor, to a second location in said surface well, said second resistive path having a horizontal length in said buried well, wherein;
• said horizontal length of said second resistive path in said buried well is chosen to provide a resistance between said first location and said second location in said surface well within a specific range of resistance values, further wherein;
• said first transistor and said second transistor are characterized as having an on current and an off current and the ratio of on current to off current in at least one of said first transistor and said second transistor is not greater than about 105, further wherein;
• at least one of said first transistor and said second transistor has an unbiased threshold voltage of between about −150 millivolts and +150 millivolts.