Multiple thickness semiconductor interconnect and method therefor

A method for forming a multiple thickness interconnect, comprising:

• providing a semiconductor structure having a substrate;
• forming a first dielectric layer over the substrate;
• forming a continuous opening in the first dielectric layer, wherein the continuous opening has a first portion, a second portion, and a third portion, wherein the first portion is shallower than the second portion and the second portion is shallower than the third portion;
• forming a conductive layer in the continuous opening;
• and
• removing the conductive layer above the first dielectric layer to leave a first current carrying layer in the first portion, a second current carrying layer in the second portion and adjoining the first current carrying layer, and a via in the third portion.

A method for forming a multiple thickness interconnect, comprising:

• providing a semiconductor structure having a substrate;
• forming a first dielectric layer over the substrate;
• forming a second dielectric layer on the first dielectric layer;
• patterning the second dielectric layer to form a patterned second dielectric layer;
• forming a third dielectric layer on the patterned second dielectric layer;
• patterning and etching the third dielectric layer selective to the second dielectric layer to form both a first portion of a continuous opening and part of a second portion of the continuous opening;
• etching the first dielectric layer to complete formation of the second portion of the continuous opening;
• forming a conductive layer in the continuous opening;
• and
• removing the conductive layer above the first dielectric layer to leave a first current carrying layer in the first portion, a second current carrying layer in the second portion and adjoining the first current carrying layer, and a via in the third portion.

A method for forming a multiple thickness interconnect, comprising:

• providing a semiconductor structure having a substrate and a first dielectric layer over the substrate;
• forming a second dielectric layer over the first dielectric layer;
• patterning the second dielectric layer to have a first area and a second area, wherein the first area is thinner than the second area;
• forming a planarized layer over the second dielectric layer;
• patterning the planarized layer to have a first opening over a first portion of the first area and a first portion of the second area;
• etching the second dielectric layer to form a second opening through to the first dielectric layer, the second opening being in the first portion of the first area and the first portion of the second area;
• forming a conductive layer in the second opening and over the second dielectric layer;
• and
• electro-chemical polishing the conductive layer above the second dielectric layer.

A method of forming a semiconductor device structure over a semiconductor substrate, comprising:

• forming a non-planar structure over the semiconductor substrate;
• depositing a removable layer over the non-planar structure of sufficient thickness to achieve a substantially planar surface on the removable layer and having at least a thickness of a first dimension;
• removing a portion of the removable layer not exceeding the first dimension to provide a reduced-thickness removable layer with a substantially planar surface;
• and
• patterning the reduced-thickness removable layer.

A method of providing an interconnect for a semiconductor, comprising:

• defining a criteria for the interconnect;
• analyzing an affect of length, width, and thickness of the interconnect;
• and
• varying the thickness of the interconnect to meet the criteria.