Integrated circuit memory devices having memory cells therein that utilize phase-change materials to support non-volatile data retention and methods of forming same

An integrated circuit memory cell, comprising:

• a semiconductor substrate;
• a first electrically insulating layer that extends on said semiconductor substrate and has a first contact hole extending therethrough;
• an electrically conductive plug that extends in the first contact hole;
• a phase-change material layer pattern having a first surface that is electrically connected to said electrically conductive plug;
• a second electrically insulating layer that extends on said phase-change material layer pattern, said second electrically insulating layer having a second contact hole therein that exposes a portion of a second surface of said phase-change material layer pattern having an area that is less than a maximum cross-sectional area of said electrically conductive plug;
• and
• an electrode that extends on said second electrically insulating layer and is electrically connected to said phase-change material layer pattern.

An integrated circuit memory cell, comprising:

• a semiconductor substrate;
• a first electrically insulating layer that extends on said semiconductor substrate and has a first contact hole extending therethrough;
• an electrically conductive plug that extends in the first contact hole;
• a first barrier layer pattern on said electrically conductive plug;
• a phase-change material layer pattern on said first barrier layer pattern;
• an oxidation resistant layer pattern on said phase-change material layer pattern;
• a second electrically insulating layer that extends on said oxidation resistant layer pattern, said second electrically insulating layer and said oxidation resistant layer pattern having a second contact hole that extends therethrough and exposes an upper surface of said phase-change material layer pattern;
• a second barrier layer that extends into the second contact hole and contacts the exposed upper surface of said phase-change material layer pattern;
• a plate electrode on said second barrier layer;
• and
• an access transistor that extends in said semiconductor substrate and has a source region that is electrically connected to said electrically conductive plug.

A non-volatile chalcogenide-based integrated circuit memory device, comprising:

• a semiconductor substrate;
• an access transistor having source and drain regions in said semiconductor substrate and a gate electrode on a surface of said semiconductor substrate;
• a first electrically insulating layer on said access transistor, said first electrically insulating layer having first and second contact holes therein that extend opposite the source and drain regions, respectively;
• first and second conductive plugs in the first and second contact holes, respectively;
• a bit line that extends on said first electrically insulating layer and is electrically connected to said second conductive plug;
• a second electrically insulating layer on said first electrically insulating layer, said second electrically insulating layer having a third contact hole therein that extends opposite the first contact hole;
• a third conductive plug that extends in the third contact hole and is electrically connected to the first conductive plug;
• a vertical stack structure comprising a first barrier layer pattern on said third conductive plug, a chalcogenide alloy pattern on said first barrier layer pattern and an oxidation resistant layer pattern on said chalcogenide alloy pattern;
• a third electrically insulating layer that covers said vertical stack structure, said third electrically insulating layer comprising a fourth contact hole therein that also extends through the oxidation resistant layer pattern and exposes a portion of an upper surface of the chalcogenide alloy pattern;
• an insulating spacer on a sidewall of the fourth contact hole;
• a second barrier layer that extends through the fourth contact hole and contacts the upper surface of the chalcogenide alloy pattern;
• and
• a plate electrode on said second barrier layer.

A method of fabricating a phase-change memory cell comprising:

• forming a data storage element on a semiconductor substrate, the data storage element having a first barrier layer pattern and a phase-change material layer pattern which are sequentially stacked;
• forming an upper interlayer insulation layer on the substrate including the data storage element;
• patterning the upper interlayer insulation layer to form a plate electrode contact hole that exposes a predetermined region of the phase-change material layer pattern;
• and
• forming a second barrier layer pattern that covers the plate electrode contact hole, the second barrier layer pattern being in contact with at least the exposed phase-change material layer pattern.

A method of fabricating phase-change memory cells comprising:

• forming a lower interlayer insulation layer on a semiconductor substrate;
• patterning the lower interlayer insulation layer to form a plurality of storage node contact holes that expose predetermined regions of the semiconductor substrate;
• forming a plurality of storage node plugs that fill the storage node contact holes;
• forming a plurality of data storage elements covering the respective storage node plugs, each of the data storage elements having a first barrier layer pattern and a phase-change material layer pattern which are sequentially stacked;
• forming an upper interlayer insulation layer on an entire surface of the substrate including the data storage elements;
• patterning the upper interlayer insulation layer to form a plurality of plate electrode contact holes that expose the respective phase-change material layer patterns;
• forming a plurality of second barrier layer plugs that fills the plate electrode contact holes;
• and
• forming a plate electrode on the substrate having the second barrier layer plugs, contact areas between the second barrier layer plugs and the phase-change material layer patterns being smaller than top surface areas of the storage node plugs.

A method of fabricating phase-change memory cells comprising:

• forming a lower interlayer insulation layer on a semiconductor substrate;
• patterning the lower interlayer insulation layer to form a plurality of storage node contact holes that expose predetermined regions of the semiconductor substrate;
• forming a plurality of storage node plugs that fill the storage node contact holes;
• forming a plurality of data storage elements covering the respective storage node plugs, each of the data storage elements having a first barrier layer pattern and a phase-change material layer pattern which are sequentially stacked;
• forming an upper interlayer insulation layer on an entire surface of the substrate including the data storage elements;
• patterning the upper interlayer insulation layer to form a plurality of plate electrode contact holes that expose the respective phase-change material layer patterns;
• forming a second barrier layer pattern that covers inner walls of the plate electrode contact holes and a top surface of the upper interlayer insulation layer;
• and
• forming a plate electrode on the second barrier layer pattern, contact areas between the second barrier layer pattern and the phase-change material layer patterns being smaller than top surface areas of the storage node plugs.