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US 2003/0208665 A1Published application
Reducing data speculation penalty with early cache hit/miss prediction
OwnerJih-Kwon Peir, Konrad Laiinventors
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Abstract
A processor may use a cache hit/miss prediction table (CPT) to predict whether a load will hit or miss and use this information to schedule dependent instructions in the instruction pipeline. The CPT may be a Bloom filter which uses a portion of the load address to index the table.
Claims20
A method comprising:
- scheduling a dependent instruction having an associated memory address;
- identifying an entry corresponding to the memory address in a table;
- reading a cache hit/miss prediction value associated with said entry;
- and
- canceling the dependent instruction in response to said cache hit/miss prediction value indicating a cache miss.
2 more elements
Apparatus comprising:
- a table including a plurality of entries, each entry having an associated cache hit/miss prediction value indicating one of a cache hit and a cache miss;
- a filter operative to generate a value from at least a portion of a memory address and to identify one of said plurality of entries corresponding to said value;
- and
- a comparator operative to detect whether a cache access for said memory address misses and to update the cache hit/miss prediction value corresponding to that memory address in response to the cache hit/miss prediction value being false.
1 more element
Apparatus comprising:
- a pipeline;
- a cache hit/miss prediction table including a plurality of entries, each entry having an associated cache hit/miss prediction value indicating one of a cache miss and a cache hit;
- a filter operative to generate a value from at least a portion of a memory address and to identify one of said plurality of entries corresponding to said value;
- and
- a scheduler operative to cancel a dependent instruction, associated with said memory address, in the pipeline and to reschedule said dependent instruction in response to the cache hit/miss prediction value associated with said memory address indicating a cache miss.
2 more elements
An article comprising a machine-readable medium including machine-executable instructions, the instructions operative to cause a machine to:
- schedule a dependent instruction having an associated memory address;
- identify an entry corresponding to the memory address in a table;
- read a cache hit/miss prediction value associated with said entry;
- and
- cancel the dependent instruction in response to said cache hit/miss prediction value indicating a cache miss.
2 more elements
Dependencies are inferred from the claim text.