Method for analyzing manufacturing data
AssigneeLSI Logic Corporation
InventorDavid Abercrombie
Life of this patent
Estimating the term…
Abstract
A method of manufacturing, e.g., integrated circuits, and of managing a manufacturing process. Product unit (circuit) variation data is collected from clustered product units (wafer sites). Collected data is grouped according to a selected manufacturing parameter. Each group is normalized for the selected manufacturing parameter. Normalized groups are combined. Normalized process data is checked for variances and the data is regrouped and renormalized until variances are no longer found. Each identified variance is correlated with a likely source. Then, each said likely source is addressed, e.g., a tool is adjusted or replaced, to minimize variances.
Claims17
A method of managing a product through a multi-step manufacturing process, clusters of product units being manufactured in parallel as a lot, each said lot including a plurality of clusters, said method comprising the steps of:
- a) collecting product variation data from product lots;
- b) grouping collected process data according to a selected manufacturing parameter;
- c) normalizing each group for said selected manufacturing parameter;
- d) combining said normalized groups to form a normalized process data collection;
- e) checking said normalized process data collection for data variances;
- and
- f) repeating steps (b) through (e) until variances are not found.
A method of manufacturing integrated circuits, said method comprising the steps of:
- a) collecting circuit variation data from wafer sites;
- b) grouping collected circuit data according to a selected manufacturing parameter;
- c) normalizing each group for said selected manufacturing parameter;
- d) combining said normalized groups to form normalized process data;
- e) checking said normalized process data for circuit variances;
- f) repeating steps (b) through (e) until circuit variances are not found;
- g) correlating each identified circuit variance with a likely process source;
- and
- h) addressing each said likely process source to minimize circuit variances.
A method as in the step (e) of checking for circuit variances of at least one of an average of wafer standard deviations, a standard deviation of wafer means or, a standard deviation of wafer standard deviations is determinative of whether all variances have been identified in step (c).
Dependencies are inferred from the claim text.