Gate technology for strained surface channel and strained buried channel MOSFET devices
AssigneeAmberWave Systems Corporation
InventorsEugene A. Fitzgerald, Richard Hammond, Matthew Currie
Life of this patent
Estimating the term…
Abstract
A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
Claims39
A method of fabricating a semiconductor device comprising:
- providing a semiconductor heterostructure, said heterostructure comprising a relaxed Si1-xGex layer on a substrate, a strained channel layer on said relaxed Si1-xGex layer, and a Si1-yGey layer;
- removing said Si1-yGey layer;
- and
- providing a dielectric layer.
A method of fabricating a semiconductor device comprising:
- providing a semiconductor heterostructure, said heterostructure comprising a relaxed Si1-xGex layer on a substrate, a strained channel layer on said relaxed Si1-xGex layer, and a Si1-yGey layer;
- removing said Si1-yGey layer to expose said strained channel layer;
- removing a portion of said strained channel layer to eliminate any residual Ge;
- and
- providing a dielectric layer.
A method of fabricating a semiconductor device comprising:
- providing a semiconductor heterostructure, said heterostructure comprising a relaxed Si1-xGex layer on a substrate, a strained channel layer on said relaxed Si1-xGex layer, a Si1-yGey spacer layer, and a S1-wGew layer;
- removing said Si1-wGew layer;
- and
- providing a dielectric layer.
A method of fabricating a semiconductor device comprising:
- providing a semiconductor heterostructure, said heterostructure comprising a relaxed Si1-xGex layer on a substrate, a strained channel layer on said relaxed Si1-xGex layer, a Si1-yGey spacer layer, a Si layer, and a Si1-wGew layer;
- removing said Si1-wGew layer to expose said Si layer;
- and
- providing a dielectric layer.
A method of fabricating a semiconductor device comprising:
- providing a semiconductor heterostructure, said heterostructure comprising a relaxed Si1-xGex layer on a substrate, a strained channel layer on said relaxed Si1-xGex layer, a Si1-yGey spacer layer, a Si layer, and a Si1-wGew layer;
- removing said Si1-wGew layer to expose said Si layer;
- and
- oxidizing said Si layer.
Dependencies are inferred from the claim text.