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AssigneeInfineon Technologies North America Corp.
InventorsDieter Rathei, Joerg Wohlfahrt, Luis G. Andrade, Robert Petter, Thomas S. Taylor, Babatunde Ashiru, Mark E. Luzar, Michael B. Sommer, Ulrich K. Zimmermann
Estimating the term…
A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.
A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon, the method comprising:
A computer program product for calculating the yield loss of semiconductor wafers, the product comprising
Dependencies are inferred from the claim text.