Semiconductor device including multi-chip

A semiconductor device comprising:

• a memory, said memory comprising:
• a first memory block including a plurality of first memory cells each having a first capacitor and a first MISFET;
• a second memory block including a plurality of second memory cells each having a second capacitor and a second MISFET;
• a first node for command signal inputting shared by said first memory block and said second memory block;
• a second node for address signal inputting;
• and a third node for data inputting;
• and
• a memory controller, said memory controller comprising:
• a four node for outputting a command signal to said memory, said four node being coupled to said first node of said memory;
• a fifth node for outputting an address to said memory, said fifth node being coupled to said second node;
• a sixth node being coupled to said third node;
• a seventh node for receiving an access request signal;
• and an eighth node for receiving an access address,
• wherein when a first access address is inputted to said eighth node in a first interval, said memory controller outputs a command signal and a first address for said first memory block from said fourth and fifth nodes, and
• wherein when said first access address is inputted to said eighth node in a second interval, said memory controller outputs a command signal and said first address for said second memory block from said fourth and fifth nodes.