Single-seed wide-swing current mirror
AssigneeExar Corporation
InventorsShin-Chung Chen, Timothy Tehmin Lu
Life of this patent
Estimating the term…
Abstract
A current mirror circuit that uses only a single seed current, and thus only a single current source. A transistor biasing circuit is connected in between the single current source and the two transistors of the first leg of the current mirror. The transistor biasing circuit provides two functions. First, the source current itself flows through the transistors of the transistor biasing circuit to the two transistors forming the first leg of the current mirror. Second, the transistor biasing circuit biases the gates of the transistors in the current mirror so that the output transistors are at the onset of saturation.
Claims8
A current mirror circuit comprising:
- fifth and sixth transistors coupled in series as an output leg of the current mirror;
- first and second transistors coupled in series as a second leg of said current mirror, a gate of said first transistor being connected to a gate of said fifth transistor, and a gate of said second transistor being connected to a gate of said sixth transistor;
- a current source;
- and
- a transistor biasing circuit coupled between said current source and said first transistor, said transistor biasing circuit providing current mirror current from said current source to said second transistor, and said transistor biasing circuit biasing said gates of said second and sixth transistors.
A current mirror circuit comprising:
- fifth and sixth transistors coupled in series as an output leg of the current mirror;
- first and second transistors coupled in series as a second leg of said current mirror, a gate of said first transistor being connected to a gate of said fifth transistor, and a gate of said second transistor being connected to a gate of said sixth transistor;
- a current source;
- a third transistor having a drain connected to the gates of said second and sixth transistors, a source connected to the gates of said first and fifth transistors, and a gate connected to said current source;
- and
- a fourth transistor having a gate and drain connected to said current source, and a source connected to said drain of said third transistor.
Dependencies are inferred from the claim text.