Vertical split gate flash memory cell and method for fabricating the same

Abstract

A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The tunnel oxide layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gate. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the control gate to serve as source and drain regions with the first doping region.

Dependencies are inferred from the claim text.