Flexible memory architecture for an embedded processor

A method of operating a computer based system, comprising:

• accessing a memory address of a physical memory system with a processing device from a cached effective address space, wherein the effective address space and a non-cached effective address space are translated to overlap the same physical address space of the physical memory system;
• accessing a memory address of the physical memory system with the processing device without accessing a cache memory system from the non-cached effective address space;
• and
• accessing a memory address of the physical memory system with at least one system device.

A machine-usable medium having machine-readable instructions stored thereon for execution by a processor to perform a method comprising:

• defining an effective memory address space with a cached address space and a non-cached address space wherein the cached address space and the non-cached address space each translate to overlap a single physical memory space;
• accessing a memory address of the physical memory space without accessing a cache memory system from the non-cached effective address space;
• and
• accessing a memory address of the physical memory space from the cached effective address space with the benefit of the cache memory system.

A method of operating a memory system, comprising:

• configuring an effective memory address space with a cached address space and a non-cached address space wherein the cached address space and the non-cached address space each translate to overlap the same address space of a physical memory system;
• accessing a memory address of the physical memory system with a processing device from the non-cached effective address space, wherein the data of the memory access is shared with at least one system device;
• and
• accessing a memory address of the physical memory system with a processing device from the cached effective address space, wherein the data of the memory access is used only by the processing device.

A method of operating a communication device, comprising:

• defining an effective memory address space with a cached address space and a non-cached address space wherein the cached address space and the non-cached address space each translate to overlap a single physical memory space;
• accessing a memory address of the physical memory space from the non-cached effective address space with a processing device;
• and
• accessing a memory address of the physical memory space from the cached effective address space with the processing device.

A memory system, comprising:

• a physical memory system with a physical memory address space;
• a memory management unit (MMU);
• wherein the MMU defines a cached effective address space and a non-cached effective address space;
• and
• wherein the cached effective address space and the non-cached effective address space are mapped by the MMU to overlap the same physical memory address space.

A computer based system, comprising:

• an embedded processing device;
• a memory system with a physical memory address space;
• at least one system device coupled to the memory system;
• a memory management unit (MMU) coupled to the embedded processing device and the memory system;
• wherein the MMU defines a cached effective address space and a non-cached effective address space;
• and
• wherein the cached effective address space and the non-cached effective address space are mapped by the MMU to overlap the same physical memory address space.

A communication device, comprising:

• at least one communication interface;
• an embedded processing device;
• a memory system with a physical memory address space;
• at least one system device coupled to the memory system;
• a memory management unit (MMU) coupled to the embedded processing device and the memory system;
• wherein the MMU defines a cached effective address space and a non-cached effective address space;
• and
• wherein the cached effective address space and the non-cached effective address space are mapped by the MMU to overlap the same physical memory address space.