Shared bit line cross-point memory array incorporating P/N junctions and method

A memory structure comprising:

• a) a first cross-point memory array, which comprises a plurality of bit lines and a first plurality of word lines arranged so that they cross over each other to form a plurality of cross-points;
• a first layer of resistive memory material interposed between the bit lines and the first plurality of word lines, and a first array of diodes formed between the resistive memory material and the first plurality of word lines, wherein each diode is located at a cross-point between the plurality of bit lines and the first plurality of word lines;
• and
• b) a second cross-point memory array, which comprises the plurality of bit lines and a second plurality of word lines arranged so that they cross over each other to form a plurality of cross-points;
• a second layer of resistive memory material interposed between the bit lines and the second plurality of word lines, and a second array of diodes formed between the resistive memory material and the second plurality of word lines, wherein each diode is located at a cross-point between the plurality of bit lines and the second plurality of word lines.

A method of manufacturing a memory structure comprising:

• a) providing a resistive cross-point memory array structure having a plurality of bit lines;
• b) depositing a layer of resistive memory material overlying the plurality of bit lines;
• c) forming an array of diode/metal electrode stacks overlying the layer of resistive memory material positioned above the plurality of bit lines;
• and
• d) patterning a plurality of top electrodes overlying the electrode stack to form a plurality of cross-points with the plurality of bit lines.