Method of manufacturing a transistor
AssigneeShindengen Electric Manufacturing Co., Ltd.
InventorsMizue Kitada, Toshiyuki Takemori, Shinji Kunori
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AssigneeShindengen Electric Manufacturing Co., Ltd.
InventorsMizue Kitada, Toshiyuki Takemori, Shinji Kunori
Estimating the term…
A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.
A transistor comprising:
A transistor comprising:
A method of manufacturing a transistor, comprising the steps of:
Dependencies are inferred from the claim text.