Method for controlling column decoder enable timing in synchronous semiconductor device and apparatus thereof

A method for controlling column decoder enable timing, comprising:

• delaying an input data write command signal for one period of a clock signal in response to the clock signal;
• and
• determining if the delayed data write command signal and a currently input data read command signal are activated at the same time,
• wherein, if the delayed data write command signal and the currently input data read command signal are not activated at the same time, generating a timing control signal delaying the clock signal for a first delay time, and if the delayed data write command signal and the currently input data read command signal are activated at the same time, generating a timing control signal delaying the clock signal for a second delay time;
• and
• activating a column decoder in response to the timing control signal.

A semiconductor memory device, comprising;

• a column decoder for decoding addresses input in response to a timing control signal and generating a column select signal corresponding to the decoding result;
• and
• a timing control signal generating circuit for generating the timing control signal,
• wherein the timing control signal generating circuit generates the timing control signal by delaying a received clock signal by an amount of time which depends on whether there is a gap between a data write command signal and a consecutive data read command signal.

A semiconductor memory device, comprising:

• a column decoder for decoding addresses input in response to a timing control signal and generating a column selection signal corresponding to the decoding result;
• and
• a timing control signal generating circuit for generating the timing control signal,
• wherein the timing control signal generating circuit generates the timing control signal by delaying the clock signal for a first delay time if a data read command is activated after the data write command is deactivated and N periods of the clock signal, and generates the timing control signal by delaying the clock signal for a second delay time if a data read command is activated within N periods of the clock signal after the data write command is deactivated.

A semiconductor memory device, comprising;

• a column decoder for decoding addresses input in response to a timing control signal and generating a column select signal corresponding to the decoding result;
• a delay circuit for delaying the data write command signal for one period of a clock signal in response to the clock signal;
• a first control circuit for receiving a data read command signal and an output signal of the delay circuit and outputting a control signal;
• and
• a second control circuit for generating the timing control signal by delaying the received clock signal for a first delay time if the control signal is activated, and for generating the timing control signal by delaying the clock signal for a second delay time if the control signal is not activated.

A semiconductor memory device, comprising;

• a column decoder for decoding addresses input in response to a timing control signal and generating column select signals corresponding to a decoding result;
• a command register for outputting a data read command signal or a data write command signal in response to the command signal;
• a delay circuit for delaying the clock signal for a first time or a second time in response to the data read command signal or the data write command signal;
• a D flip-flop for delaying the data write command signal for one period of the clock signal;
• a detecting circuit for receiving an output signal of the data read command signal and an output of the D flip flop and outputting a detecting signal;
• and
• an output circuit for outputting a timing control signal having a first delay time if the detecting signal is not activated, and for outputting a timing control signal having a second delay time if the detecting signal is activated.