Semiconductor device containing oxide/nitride/oxide dielectric layer and method of forming the same

A semiconductor device comprising:

• a semiconductor substrate;
• a patterned floating gate formed on the semiconductor substrate, the patterned floating gate having upper and side parts and corners;
• and
• a dielectric layer comprising:
• (i) a first oxide layer formed by a low pressure chemical vapor deposition (LPCVD) process;
• (ii) a nitride layer formed over the first oxide layer;
• and (iii) a second oxide layer deposited over the nitride layer and being formed by a low pressure chemical vapor deposition (LPCVD) process, whereby the dielectric layer is deposited over the semiconductor substrate and the patterned floating gate,
• wherein the ratio of the thickness of the first oxide layer in the upper and side parts of the patterned floating gate to the thickness of the first oxide layer in the corners of the patterned floating gate does not exceed 1.4.

A method of fabricating a semiconductor device having a composite dielectric layer comprised of a first oxide layer, a nitride layer and second oxide layer, comprising:

• providing a semiconductor substrate;
• depositing the first oxide layer on the semiconductor substrate by a LPCVD process at a temperature of from about 650 to about 800° C., and at a pressure of from about 1 to about 100 Pa;
• subjecting the substrate to first annealing under an atmosphere of N2O or NO or NH3 to form a surface layer in the first oxide layer containing less than 5% nitrogen;
• depositing the nitride layer on the first oxide layer;
• depositing the second oxide layer on the nitride layer by a LPCVD process at a temperature of from about 650 to about 800° C., and at a pressure of from about 1 to about 100 Pa;
• and
• subjecting the substrate to a second annealing under an atmosphere of N2O or NO or NH3 to form a surface layer in the second oxide layer containing less than 5% nitrogen.

A method of fabricating a nonvolatile memory device having stacked gate memory cells composed of floating gates, and control gates formed over the floating gates with a dielectric interlayer interposed therebetween, comprising:

• providing a semiconductor substrate;
• forming element isolation regions to define active regions in the semiconductor substrate;
• depositing a floating gate polysilicon layer over the substrate including the element isolation regions;
• forming the dielectric interlayer;
• and
• depositing a control gate polysilicon layer over the dielectric interlayer, wherein forming the dielectric interlayer comprises:
• depositing a first oxide layer on the floating gate and the substrate by a LPCVD process at a temperature of from about 650 to about 800° C., and at a pressure of from about 1 to about 100 Pa;
• subjecting the substrate to a first annealing under an atmosphere of N2O or NO or NH3 to form a surface layer in the first oxide layer containing less than 5% nitrogen;
• depositing a nitride layer on the first oxide layer;
• depositing a second oxide layer on the nitride layer by a LPCVD process at a temperature of from about 650 to about 800° C., and at a pressure of from about 1 to about 100 Pa;
• and
• subjecting the substrate to a second annealing under an atmosphere of N2O or NO or NH3 to form a surface layer in the second oxide layer containing less than 5% nitrogen.