Semiconductor device and manufacturing method thereof

A semiconductor device comprising:

• an SOI substrate configured by providing a mono-crystalline semiconductor layer through an embedded insulation layer on a first conductivity type semiconductor substrate of which the surface is provided with a first impurity diffused layer of the first conductivity type and a second impurity diffused layer of the second conductivity type;
• a MIS field-effect transistor provided within a device region defined by isolating said mono-crystalline semiconductor layer with a device isolation region, and having a gate electrode;
• first and second openings penetrating said device isolation region and said embedded insulation layer and reaching said first impurity diffused layer of said semiconductor substrate;
• third and fourth openings penetrating said device isolation region and said embedded insulation layer and reaching said second impurity diffused layer of said semiconductor substrate;
• first and fourth polysilicon substrate electrodes of the first conductivity type, taking such a configuration as to fill and cover said first and fourth openings, and taken out up to the surface flush with said gate electrode;
• and
• second and third polysilicon substrate electrodes of the second conductivity type, taking such a configuration as to fill and cover said second and third openings, and taken out up to the surface flush with said gate electrode,
• wherein first and second diodes for an electrostatic protection are composed respectively of a group of said first polysilicon electrode, said first impurity diffused layer and said second polysilicon electrode, and a group of said third polysilicon electrode, said second impurity diffused layer and said fourth polysilicon electrode.

A method of manufacturing a semiconductor device, comprising:

• providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type;
• forming an opening penetrating said device isolation region and said embedded insulation layer and reaching said semiconductor substrate;
• depositing polysilicon on said SOI substrate and within said opening and providing a gate electrode and a substrate electrode of said MIS type field-effect transistor by executing the patterning thereon;
• and
• implanting impurities into said gate electrode and said substrate electrode.

A method of manufacturing a semiconductor device, comprising:

• providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type;
• providing a first polysilicon layer on the entire surface;
• forming an opening penetrating said first polysilicon layer, said device isolation region and said embedded insulation layer and reaching said semiconductor substrate;
• providing a second polysilicon layer on the entire surface to cover said opening;
• providing a substrate electrode by patterning said first and second polysilicon layers;
• and
• implanting an impurity into said substrate electrode.