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US 2003/0201463 A1Published application
Automatic layout and wiring method for semiconductor integrated circuit
OwnerNobuyuki Ikeda, Kazuhiro Takahashiinventors
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Abstract
A net including paths having a long inter-path distance is designated as one to which a specific design rule for defining a wide wire and a wide wiring interval is applied. After the designation, optimization of a circuit such as a change in cell drivability and insertion of a driver cell is performed so as to satisfy a timing condition designated by timing restriction information.
Claims8
An automatic layout and wiring method for a semiconductor integrated circuit, the method comprising steps of:
- arranging a plurality of cells included in LSI circuit connection information in a wiring area based on timing restriction information and a design rule including a specific design rule for defining a wide wire and a wide wiring interval and a regular design rule;
- extracting a wiring distance between signal paths connected to the arranged cells as state holding circuits;
- designating a wiring net to which the specific design rule is applied based on the extracted inter-path distance;
- extracting loads of wires based on the inter-path distance and the design rule for the designated wiring net;
- changing a cell group in the path into an optimum circuit based on the wiring load of the signal path between the state holding circuits;
- and
- conducting detailed wiring of the signal wires in the optimized cell group based on the designated design rule.
4 more elements
Dependencies are inferred from the claim text.