Gate-coupled MOSFET ESD protection circuit
AssigneeWinbond Electronics Corp.
InventorsShi-Tron Lin, Wei-Fan Chen
Life of this patent
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Abstract
A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.
Claims14
An ESD protection circuit providing an ESD path from a first to a second node when an ESD voltage applied to the first node, the circuit comprising:
- a timing-control circuit outputting a first voltage when the ESD voltage is applied to the first node;
- a voltage divider outputting a second voltage divided from the ESD voltage when activated by the first voltage output from the timing-control circuit;
- and
- a shunt transistor having a drain coupled to the first node, a source coupled to the second node and a gate-coupled to the voltage divider, and entering into a snapback to provide the ESD path from the drain to the source when the ESD voltage is applied to the first node.
An ESD protection circuit providing an ESD path from a first to a second power bus when an ESD voltage applied to the first power bus, the circuit comprising:
- a timing-control circuit outputting a first voltage when the ESD voltage is applied to the first power bus;
- a voltage divider outputting a second voltage divided from the ESD voltage when activated by the first voltage output from the timing-control circuit;
- and
- a shunt transistor having a drain coupled to the first power bus, a source coupled to the second power bus and a gate-coupled to the voltage divider, and entering into a snapback to provide the ESD path by the drain and the gate receiving the ESD and the second voltages when the ESD voltage is applied to the first power bus.
An ESD protection circuit providing an ESD path from a pad to a second power bus when an ESD voltage is applied to the pad, the ESD voltage coupled through a PN junction to a first power bus, the circuit comprising:
- a timing-control circuit outputting a first voltage when the ESD voltage is applied to the pad;
- a voltage divider outputting a second voltage divided from the ESD voltage when activated by the first voltage output from the timing-control circuit;
- and
- a shunt transistor having a drain coupled to the pad, a source coupled to the second power bus and a gate-coupled to the voltage divider, and entering into a snapback to provide the ESD path from the drain to the source when the ESD voltage is applied to the pad.
An ESD protection circuit providing an ESD path to a second node when an ESD voltage applied to one of first nodes, the circuit comprising:
- a timing-control circuit outputting a first voltage when the ESD voltage is applied to one of the first nodes;
- a voltage divider outputting a second voltage divided from the ESD voltage when activated by the first voltage output from the timing-control circuit;
- and
- a shunt transistor having a drain coupled to the first nodes, a source coupled to the second power bus and a gate-coupled to the voltage divider, and entering into a snapback to provide the ESD path when the drain and the gate receiving the ESD and the second voltages and the ESD voltage is applied to one of the first nodes.
Dependencies are inferred from the claim text.