Array-based architecture for molecular electronics
AssigneesCalifornia Institute of Technology, President and Fellows of Harvard College
InventorsAndre DeHon, Charles M. Lieber
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Abstract
An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.
Claims64
An architecture for nanoscale electronics comprising:
- arrays of crossed nanoscale wires, each array comprising a plurality of crosspoints between nanoscale wires, the crosspoints being selectively programmable, wherein nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the one array and the other arrays;
- and
- nanoscale signal restoration elements, allowing an output of a first array to be used as an input to a second array, wherein signal restoration occurs without routing of the signal to non-nanoscale wires.
A circuit comprising:
- a plurality of arrays having first and second sets of address lines and connections between the first and second sets of address lines;
- and
- a plurality of driving devices for the plurality of arrays, the driving devices having third and fourth sets of address lines and connections between the third and fourth sets of address lines,
- wherein the driving devices have a first condition in which they act as decoders for the arrays, and a second condition in which they act as signal restoring devices for the arrays.
A method of driving a plurality of arrays having first and second sets of address lines and connections between the first and second sets of address lines, the method comprising:
- providing a plurality of driving devices for the plurality of arrays, the driving devices having third and fourth sets of address lines and connections between the third and fourth sets of address lines, the driving devices having a first condition in which the driving devices act as decoders for the arrays, and a second condition in which the driving devices act as signal restoring devices for the arrays.
A method for assembly of arbitrary boolean logic computations at sublithographic scales, the method comprising:
- providing sublithographic-scale arrays performing a predetermined logic function;
- interconnecting the arrays;
- and
- customizing the arrays to perform the logic function and signal routing.
Dependencies are inferred from the claim text.