Dynamic scan circuitry for A-phase

A clock buffer circuit comprising:

• a series connection of transistors coupled between a first node and ground, the series connection of transistors including at least a first transistor and a second transistor, wherein the first transistor has a first control node coupled to receive a first signal corresponding to a functional clock and the second transistor has a second control node controlled by an inverse of the first signal, the functional clock operating during functional operation;
• a third transistor coupled to the first node and having a third control node controlled by an inverse of a first input;
• and
• a fourth transistor coupled in parallel with at least the second transistor and having a fourth control node controlled by a logic circuit responsive to the first input and a second input.

In an apparatus having a first dynamic logic circuit having an output node on which a scan value is provided during scan;

• a second dynamic logic circuit having an input coupled to the output node of the first dynamic logic circuit, wherein the first dynamic logic circuit and the second dynamic logic circuit are in a first dynamic phase during functional operation;
• one or more third dynamic logic circuits, wherein one of the third dynamic logic circuits has an input coupled to receive a dynamic logic signal responsive to the second dynamic logic circuit, wherein the third dynamic logic circuits are in a second dynamic phase during functional operation, a method comprising:
• generating at least one evaluate pulse on a first clock responsive to a scan mode signal and a scan clock, wherein the scan mode signal is indicative of whether or not scan is active, and wherein the first clock controls at least evaluation of the second dynamic logic circuit;
• generating at least one evaluate pulse on a second clock controlling at least evaluation of the one or more third logic circuits;
• and
• sampling the output of the third dynamic logic circuits subsequent to generating the at least one evaluate pulse on the first clock and subsequent to generating at least one evaluate pulse on the second clock, wherein the output is responsive to the scan value on the output node of the first dynamic logic circuit.