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US 2003/0200476 A1Published application
Method for improving a timing margin in an intergrated circuit by setting a relative phase of receive/transmit and distributed clock singls
AssigneeIntel Corporation
InventorKEITH E. DOW
Life of this patent
Estimating the term…
Abstract
An embodiment of the invention includes an apparatus that has a first clock on a memory controller hub that is set to a first clock receive time and a second clock on the memory controller hub set to a first clock transmit time. A first data is sent from the memory to the memory controller hub. A second data is sent from the memory to the memory controller hub wherein the second data is checked. At least one of the first clock and the second clock has at least one of a second clock receive time and a second clock transmit time adjusted.
Claims17
An apparatus comprising:
- a first clock on a memory controller hub is set to a first clock receive time;
- a second clock on the memory controller hub is set to a clock transmit time;
- a first data is sent to memory from the memory controller hub;
- a second data is sent from the memory to the memory controller hub;
- the second data is checked;
- and
- at least one of the first clock and the second clock has at least one of a second clock receive time and a second clock transmit time is adjusted.
4 more elements
An apparatus comprising:
- a first clock on a memory controller hub is set to a first clock receive time and first clock transmit time;
- a first positive data skew point and to a first negative data skew point;
- a first midpoint is determined from the first positive data skew point and the negative data skew point are determined.
A method comprising:
- setting a first clock to a first clock receive time;
- setting a second clock to a clock transmit time;
- sending a first data from a memory controller hub to memory;
- sending a second data to the memory controller hub;
- checking the second data;
- and
- setting at least one of a first clock and the second clock to at least one of a second clock receive time and a second clock transmit time.
4 more elements
Dependencies are inferred from the claim text.