Providing a register file memory with local addressing in a SIMD parallel processor

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, a method for providing said local addressing comprising:

• providing a first address of a row of data cells in a first data column;
• writing to a plurality of select cells in a first select column by:
• activating a corresponding select cell write line, and
• driving a plurality of master row select lines with a first decoded address that selects said row of data cells in said first data column that corresponds to said first select column;
• providing a second address of a row of data cells in a second data column in said memory;
• writing to a plurality of select cells in a second select column by:
• activating a corresponding select cell write line, and
• driving said plurality of master row select lines with a second decoded address that selects said row of data cells in said second data column that corresponds to said second select column;
• driving said plurality of master row select lines with a binary “1;” and
• reading data from or writing data to:
• said row of data cells in said first data column when a corresponding select cell and master row select line are binary “1,” and
• said row of data cells in said second data column when a corresponding select cell and master row select line are binary ”1.”

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, a method for providing said local addressing comprising:

• providing decode logic that accepts as input an address in said memory from which data is to be read or to which data is to be written;
• dividing said memory into a plurality of data columns, wherein each of said plurality of data columns comprises a plurality of rows of data cells;
• providing a select column for each of said plurality of data columns, wherein each select column comprises a plurality of select cells, wherein each of said plurality of select cells corresponds to a row of data cells;
• providing a select cell write line for each select column;
• and
• providing a master row select line from each output of said decode logic to a select cell in each select column, wherein each output corresponds to an address of a row of data cells in each of said plurality of data columns to which a corresponding master row select line is provided.

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, a method for providing local addressing comprising:

• providing an address in said memory;
• activating a select cell write line;
• driving a master row select line with a decoded address bit;
• writing to a select cell corresponding to said decoded address bit and said select cell write line;
• activating said master row select line;
• and
• performing an operation on a row of data cells corresponding to said select cell and said activated master row select line.

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, a method for providing local addressing comprising:

• providing a first address in said memory;
• activating a select cell write line whose corresponding data column is associated with said first address;
• driving a plurality of master row select lines with a first decoded address;
• writing to a plurality of select cells corresponding to said first decoded address and said select cell write line;
• providing a second address in said memory;
• activating a different select cell write line whose corresponding data column is associated with said second address;
• driving a plurality of master row select lines with a second decoded address;
• writing to a plurality of select cells corresponding to said second decoded address and said different select cell write line;
• activating said plurality of master row select lines;
• and
• performing an operation on a row of data cells in each data column whose corresponding select cell is set to binary “1.”

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising:

• a decoder comprising:
• n inputs coupled to receive one bit each of an address from which data is to be read or to which data is to be written, and
• 2n outputs;
• a plurality of select columns in said memory, wherein each of said plurality of select columns comprises a plurality of select cells, wherein each of said plurality of select cells comprises:
• a first input coupled to receive one of said 2n outputs of said decoder via a master row select line,
• a second input coupled to receive a value from a select cell write line, and
• an output;
• a plurality of AND gates, wherein each of said plurality of AND gates comprises:
• a first input coupled to receive an output of a select cell,
• a second input coupled to receive a value from a corresponding master row select line, and
• an output;
• and
• a plurality of data columns in said memory, wherein each of said plurality of data columns comprises a plurality of rows of data cells, each row of data cells corresponds to one select cell and each row of data cells comprises:
• an input coupled to receive an output of a corresponding AND gate, and
• a data path from which data is be read or to which data is to be written.

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising:

• a register file memory, wherein said register file memory allows each of said plurality of processing elements to read data from or to write data to a different address in register file memory;
• a control logic and sequencer, wherein said control logic and sequencer controls data flow;
• an interconnect, wherein said interconnect allows data flow between said plurality of processing elements;
• and
• a memory buffer register, wherein said memory buffer register stores data from said plurality of processing elements to send to a main memory and stores data from said main memory to send to said plurality of processing elements.

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, an apparatus for providing local addressing comprising:

• an address decoder that outputs master row select lines;
• a data column comprising rows of data cells;
• a select column comprising select cells, wherein each select cell:
• corresponds to a row of data cells in said data column, and
• is coupled to receive as input a corresponding master row select line that is associated with an address of a corresponding row of data cells;
• a select cell write line connected to each select cell in said select column;
• and
• a plurality of AND gates associated with said select column, wherein each AND gate is coupled to a corresponding select cell and master row select line.

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising:

• means for providing an address of a row of data cells in said memory;
• means for writing to a select cell by:
• driving a select cell write line, and
• driving a master row select line with a decoded address bit that signals when said row of data cells corresponding to said master row select line is to be read or to be written, wherein said row of data cells corresponds to said select cell;
• means for driving said master row select line with a binary “1;” and
• means for reading data from or writing data to said row of data cells when said select cell and said master row select line are binary “1.”

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising:

• means for providing decode logic that accepts as input an address in said memory from which data is to be read or to which data is to be written;
• means for dividing said memory into a plurality of data columns, wherein each of said plurality of data columns comprises a plurality of rows is of data cells;
• means for providing a select column for each of said plurality of data columns, wherein each select column comprises a plurality of select cells, wherein each of said plurality of select cells corresponds to a row of data cells;
• means for providing a select cell write line for each select column;
• and
• means for providing a master row select line from each output of said decode logic to a select cell in each select column, wherein each output corresponds to an address of a row of data cells in each of said plurality of data columns to which a corresponding master row select line is provided.

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing local addressing comprising:

• means for providing an address in said memory;
• means for activating a select cell write line;
• means for driving a master row select line with a decoded address bit;
• means for writing to a select cell corresponding to said decoded address bit and said select cell write line;
• means for activating said master row select line;
• and
• means for performing an operation on a row of data cells corresponding to said select cell and said activated master row select line.

For use in a memory with global addressing and local addressing, wherein said global addressing allows a plurality of processing elements to read data from or to write data to a location in said memory and said local addressing allows said plurality of processing elements to read data from or to write data to different locations in said memory, apparatus for providing said local addressing comprising:

• a register file memory means, wherein said register file memory allows each of said plurality of processing elements to read data from or to write data to a different address in register file memory;
• a control logic and sequencer means, wherein said control logic and sequencer controls data flow;
• an interconnect means, wherein said interconnect allows data flow between said plurality of processing elements;
• and
• a memory buffer register means, wherein said memory buffer register stores data from said plurality of processing elements to send to a main memory and stores data from said main memory to send to said plurality of processing elements.