US 2003/0200362 A1Published application

Direct memory access controller

AssigneeFujitsu Limited

InventorsYuusuke Hayashi, Masaaki Tani

Life of this patent

Estimating the term…

Loading patent…

Abstract

A transfer destination address generator includes an arithmetic device that calculates a difference between a transfer destination address and a transfer source address, a difference holding register that stores the difference, and an arithmetic device that calculates the transfer destination address based on the difference stored in the difference holding register, and on the transfer source address. A transfer source address generator includes a transfer source address register that stores a present value of the transfer source address, and a transfer source reload register that stores an initial value of the transfer source address.

Claims12

Dependent claims

A direct memory access controller, in which an additive value or a subtractive value of a transfer destination address is equal to an additive value or a subtractive value of a transfer source address, comprising:

a transfer source address storing unit that stores a present value of the transfer source address;
a transfer source reload storing unit that stores an initial value of the transfer source address;
a first difference calculating unit that obtains a difference between the initial value of the transfer source address and an initial value of the transfer destination address;
a difference storing unit that stores the difference obtained by the first difference calculating unit;
and
a second difference calculating unit that calculates a present value of the transfer destination address based on the difference stored in the difference storing unit and the present value of the transfer source address stored in the transfer source address storing unit.

3 more elements

a transfer destination address storing unit that stores a present value of the transfer destination address;
a transfer destination reload storing unit that stores an initial value of the transfer destination address;
a first difference calculating unit that obtains a difference between the initial value of the transfer destination address and an initial value of the transfer source address;
a difference storing unit that stores the difference obtained by the first difference calculating unit;
and
a second difference calculating unit that calculates a present value of the transfer source address based on the difference stored in the difference storing unit and the present value of the transfer destination address stored in the transfer destination address storing unit.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/370,523Filed 24 Feb 2003
Priority: JP 2002-11975222 Apr 2002
Published: 23 Oct 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 13/28
For access to input/output bus: using burst mode transfer, e.g. direct memory access DMA, cycle steal
Y02D 10/00
Energy efficient computing
G06F
Computing and data processing
Y02D
Climate change mitigation technologies in information and communication technologies [ict], i.e. information

Family

US 6,763,401 B2Related patent
US 2003/0200362 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key