Method, apparatus, and system for maintaining conflict-free memory address space for input/output memory subsystems

An apparatus comprising:

• a first address translation unit programmed for a minimum amount of memory addresses required to accept control transactions on a first bus;
• a second address translation unit programmed to a memory address range that corresponds to an amount of local memory for caching operations between the first I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;
• logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit;
• and
• logic to dynamically alter a data flow between the first I/O interconnect device and the host such that data from the first I/O interconnect device is transferred to host via the local memory of the first I/O processor, if the reply address overlaps with the memory address range for the second address translation unit.

A system comprising:

• a host processor coupled to transmit data to and receive data from one or more input/output (I/O) devices;
• and
• an input/output (I/O) processor coupled to the host processor via a host bus to manage input/output operations with respect to the one or more I/O devices, the I/O processor including:
• a first address translation unit programmed for a minimum amount of memory addresses required to accept control transactions on a first bus;
• a second address translation unit programmed to a memory address range that corresponds to an amount of local memory for caching operations between the I/O processor and a first I/O interconnect device and an amount of memory required by the first I/O interconnect device;
• logic to determine, upon receiving an incoming host request, whether a reply address corresponding to the host request overlaps with the memory address range programmed for the second address translation unit;
• and
• logic to dynamically alter a data flow between the first I/O interconnect device and the host processor such that data from the first I/O interconnect device is transferred to host processor via the local memory of the I/O processor, if the reply address overlaps with the memory address range for the second address translation unit.