Minimally spaced MRAM structures
AssigneeMicron Technology, Inc.
InventorsD. Mark Durcan, Trung T. Doan, Roger Lee, Dennis Keller, Ren Earl
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Abstract
A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.
Claims72
A method of forming at least one magnetic random access memory cell structure, said method comprising:
- forming a mask layer having a predetermined pattern over an insulating layer, said predetermined pattern including first photoresist areas each formed of a masking material of a predetermined width;
- reducing said predetermined width of said first photoresist areas to form second reduced-width photoresist areas;
- forming at least one groove in said insulating layer using said second reduced-width photoresist areas as a mask;
- forming a conductive layer in said at least one groove;
- and
- forming a first magnetic layer over said conductive layer.
A method of forming a plurality of magnetic random access memory cells over an insulating layer of a semiconductor substrate, said method comprising:
- forming a photoresist layer defining a predetermined pattern over said insulating layer, said photoresist layer including first photoresist areas having a predetermined width;
- reducing said predetermined width of said first photoresist areas to form second reduced-width photoresist areas;
- forming a plurality of grooves in said insulating layer using said second reduced-width photoresist areas as a mask;
- forming a plurality of bit line conductive layers in said grooves, said bit line conductive layers being spaced apart from each other by less than 0.20 μm;
- forming a plurality of first magnetic layers over respective bit line conductive layers;
- forming a plurality of second magnetic layers spaced along said first magnetic layers;
- and
- forming a plurality of word layers over respective sets of second magnetic layers, said word lines running substantially orthogonal to said first magnetic layers.
A magnetic random access memory structure comprising:
- a plurality of longitudinally extending conductive bit lines formed over an insulating layer of a semiconductor substrate, said plurality of bit lines being spaced apart from each other by a distance of less than about 0.20 μm;
- and
- respective first magnetic layers over said conductive bit lines.
A memory device comprising:
- at least one magnetic random access memory cell, said magnetic random access memory cell comprising a first ferromagnetic layer formed over a bit line conductor, a second ferromagnetic layer formed over said first ferromagnetic layer, a nonmagnetic layer between said first and second ferromagnetic layers, and a word line in contact with said second ferromagnetic layer, said memory cell being arranged so that said bit line conductor is spaced from an adjacent bit line conductor by a distance of less than or equal to about 0.20 μm.
A processor-based system, comprising:
- a processor;
- and
- an integrated circuit coupled to said processor, said integrated circuit including a plurality of magnetic random access memory cells, each of said magnetic random access memory cells including a first ferromagnetic layer formed over a bit line conductor, a second ferromagnetic layer formed over said first ferromagnetic layer, a nonmagnetic layer between said first and second ferromagnetic layers, and a word line in contact with said second ferromagnetic layer, said memory cell being arranged so that said bit line conductor is spaced from an adjacent bit line conductor by a distance less than or equal to about 0.25 μm.
Dependencies are inferred from the claim text.