Method of fabricating patterns with a dual damascene process
AssigneeNEC Electronics Corporation
InventorMasashi Fujimoto
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AssigneeNEC Electronics Corporation
InventorMasashi Fujimoto
Estimating the term…
A via hole 18 is opened in an interlayer insulating film 17, which covers a lower layer interconnect 12, a protective film 19 is embedded on the base portion of the via hole 18, and a soluble resin 20, which dissolves in a resist developing fluid under unexposed conditions, is further embedded thereupon. On this basis, a photoresist 21 is applied, and this photoresist 21 is subjected to an exposure and a development process so as to form a resist pattern 21a, which has an aperture window in a region including the via hole. Upon formation of an interconnective trench in the interlayer insulating film 17 utilizing the resist pattern 21a, a dual damascene structure is formed by embedding a metallic material into the vial hole and interconnective trench.
A method of fabricating patterns with a dual damascene process, comprising the steps of:
Dependencies are inferred from the claim text.
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For dual-damascene structures: involving intermediate temporary filling with material
For dual-damascene structures: wherein via-level dielectrics are compositionally different than trench-level dielectrics
Generic packages, interconnections, connectors or other constructional details of devices covered by
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1. Field of the Invention
The present invention relates to a dual damascene process. It is particularly related to a method of fabricating a pattern of a via and an interconnective trench with a via-first method, namely by first forming the via so as to connect upper and lower layers with interconnect.
2. Description of the Prior Art
FIG. 1A through FIG. 1D depict cross-sections illustrating a conventional example of a pattern formation process in order of steps thereof;
FIG. 2A through FIG. 2C depict cross sections continuing after FIG. 1D to illustrate the conventional example of the pattern formation process in order of steps thereof;
FIG. 3 depicts a top view of a dual damascene structure of a first embodiment of the present invention;
Hereinafter, several embodiments of a pattern formation method of the dual damascene process of the present invention will be given and described in detail with reference to the drawings.
FIG. 3 depicts a top view of a dual damascene pattern formed according to the first embodiment of the pattern formation method of the present invention. As illustrated in FIG. 3, a lower layer interconnect 12 of a dual damascene, which applies the first embodiment of the pattern formation method of the present invention, is formed into a predetermined pattern, and upon an interlayer insulating film 17 that covers this lower layer interconnect 12, a trench interconnect, which has a predetermined pattern partially crossing the lower layer interconnect 12, is formed as an upper interconnect 25.
At the crossing portions of the dual damascene, a via 24 is then extended downwards from the upper interconnect 25, and upon contact with the lower layer interconnect 12, the lower layer interconnect 12 and upper interconnect 25 are electrically connected through the via.