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US 2003/0198878 A1Published application
Method of manufacturing semiconductor device
AssigneeFujitsu Limited
InventorTakayoshi Minami
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AssigneeFujitsu Limited
InventorTakayoshi Minami
Estimating the term…
A resist pattern of a resist film is formed by exposing the resist film using a gate electrode forming mask (a Levenson phase shift mask), and developing the resist film. An antireflection film is etched using the resist pattern as an etching mask, and the resist pattern and the antireflection film are trimmed. The manner of this trimming is not to etch a hard mask made of an inorganic material, but to etch the resist pattern and the antireflection film made of an organic material. Since a region consistent with a wiring pattern of the hard mask is covered by the resist pattern completely, breaking down and retraction of the wiring are prevented.
A method of manufacturing a semiconductor device in which a first region and a second region narrower in width than that in said first region exist in a film, said method comprising the steps of:
A method of manufacturing a semiconductor device in which a first region and a second region narrower in width than that in said first region exist in a film, said method comprising the steps of:
Dependencies are inferred from the claim text.
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Of masks comprising organic materials: of organic photoresist masks
Etching of wafers, substrates or parts of devices: using masks for conductive or resistive materials
Characterised by the conductor: the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
Generic processes or apparatus for the manufacture or treatment of devices covered
Term end not estimated
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-120991, filed on Apr. 23, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a step of patterning one layer using a plurality of reticles.
FIG. 1A and FIG. 1B are plan views showing patterns of a polycrystalline silicon layer which will be formed according to an embodiment of the present invention;
FIG. 2A and FIG. 2B are plan views showing patterns for wiring formation masks used in the embodiment of the present invention;
FIG. 3A and FIG. 3B are plan views showing patterns for gate electrode formation masks used in the embodiment of the present invention;
A method of manufacturing a semiconductor device relating to an embodiment of the present invention will be explained in detail hereinafter referring to attached drawings. FIG. 1A and FIG. 1B are plan views showing a patterns of polycrystalline silicon layer which will be formed according to the embodiment of the present invention. A first pattern shown in FIG. 1A and a second pattern shown in FIG. 1B are included in the patterns of the polycrystalline silicon layer.
As shown in FIG. 1A, the first pattern includes three gate electrodes 1a to 1c, all extending in the same direction. The gate electrodes 1a and 1b extend on one linear line. Further, the gate electrodes 1b and 1c locate on one linear line perpendicular to the direction along which the gate electrodes 1a to 1c extend. Wirings 2 extending in a manner to alienate from respective gate electrodes are connected to both ends of the respective gate electrodes 1a to 1c. Further a wiring 2a extending perpendicularly to the direction along which the gate electrodes 1a to 1c extend is connected to the wiring 2 connected between the gate electrodes 1a and 1b in a manner to alienate from the gate electrode 1c. Further, a wiring 2b extending in parallel to the gate electrodes 1a to 1c is disposed at an intermediate position between the gate electrodes 1b and 1c. Incidentally, these polycrystalline silicon layers are formed on a semiconductor substrate 10 via a gate insulating film (not shown).
As shown in FIG. 1B, the second pattern includes one piece of gate electrode 1d. Similarly to the first pattern, the wirings 2 are connected to both ends of the gate electrode 1d. Wirings 2c and 2d extending in the direction to alienate from the gate electrode 1d are arranged at a position apart from the gate electrode 1d.