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US 2003/0197248 A1Published application
Method for making a multi-die chip
AssigneeMEMX, Inc.
InventorsJeffry Joseph Sniegowski, Murray Steven Rodgers
Life of this patent
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Abstract
The present invention generally relates to a die perimeter region of a die having a microelectromechanical assembly fabricated thereon. This die perimeter region may be configured to facilitate electrically interconnecting adjacent die on a wafer. Moreover, this die perimeter region may be configured to facilitate separating the die from a wafer.
Claims20
A method for fabricating a chip, comprising the steps of:
- forming a first oxide layer over a substrate;
- forming a first die boundary channel in said first oxide layer that extends down through said first oxide layer and to said substrate;
- forming a dielectric layer over said first oxide layer and within at least a lower portion of said first die boundary channel;
- defining first and second die on opposite sides of at least a portion of said first die boundary channel, wherein each said die comprises a microelectromechanical assembly;
- and
- separating said first die from said second die at least along a portion of said first die boundary channel.
3 more elements
A method for fabricating a chip, comprising the steps of:
- forming a plurality of rows and columns of die on a wafer, wherein each of said die is identical and comprises a first microelectromechanical assembly;
- and
- electrically interconnecting at least one of each adjacent pair of said die in each of said columns and each said adjacent pair of said die in each of said rows such that a first chip of a first number of said die may be formed from said wafer and that a second chip of a second number of said die may be formed from said wafer, wherein said first number is different from said second number.
Dependencies are inferred from the claim text.