ESD protection circuit sustaining high ESD stress

An ESD protection circuit, suitable for application of an integrated circuit (IC), comprising:

• an ESD detection circuit, for detecting an ESD event and providing triggering current;
• a bipolar junction transistor (BJT), comprising:
• a base, formed by a first doped region of a first conductivity type, coupled to the ESD detection circuit through a substrate-triggering region;
• and
• a collector and an emitter, respectively formed by a second doped region and a third doped region, both of a second conductivity type and formed on the first doped region, the emitter coupled to a power line and the collector coupled to a pad;
• and
• a dummy gate structure, to separate the second doped region is from the substrate-triggering region, and comprising a conductive gate, part of the conductive gate having dopant of the first conductivity type and the other part of the conductivity gate having dopant of the second conductivity type;
• wherein during normal circuit operations, the base is coupled to the power line, and when an ESD event occurs at the pad, the BJT is triggered by the triggering current to release ESD current.

A structure of an ESD protection component, suitable for application on a substrate, comprising:

• a guard ring of a first conductivity type, formed on a first doped region of the first conductivity type on the substrate and coupled to a power line;
• and
• an active region, formed on the surface of the first doped region and surrounded by the guard ring, comprising:
• at least two gate structures formed approximately in parallel across the active region;
• at least one annular dummy gate structure, formed between the gate structures;
• at least a substrate-triggering region of the first conductivity type to provide triggering current, formed on the active region surrounded by the annular dummy gate structure and coupled to an ESD detection circuit;
• at least one source region of the second conductivity type, defined by the gate structures on the active region and coupled to the power line;
• and
• at least one drain region of the second conductivity type, defined by the gate structures and the annular dummy gate structure on the active region, and coupled to a pad;
• wherein during normal circuit operations, the first doped region is coupled to the power line through the guard ring;
• and, during an ESD event, triggering current is provided by the ESD detection circuit to trigger at least two bipolar-junction-transistors (BJTs) parasitic under the gate structures to release ESD stress.

A structure of an ESD protection component, suitable for application on a substrate, comprising;

• a plurality of metal-oxide-semiconductor field-effect-transistor (MOSFET) cells arranged into a matrix, each MOSFET cell comprising:
• an annular dummy gate structure, formed on a first doped region of a first conductivity type on the substrate;
• a substrate-triggering region of the first conductivity type to provide triggering current, formed on the first doped region surrounded by the annular dummy gate structure and coupled to an ESD detection circuit;
• a drain region of a second conductivity type, formed on the first doped region surrounding the annular dummy gate structure and coupled to a pad;
• a gate structure, formed on the first doped region surrounding the drain region;
• a source region of the second conductivity type, formed on the first doped region surrounding the gate structure and coupled to a power line;
• and
• a guard ring of the first conductivity type, formed on the first doped region and coupled to the power line;
• wherein during normal circuit operations, the first doped region is coupled to the power line through the guard ring, and during an ESD event, triggering current is provided by the ESD detection circuit to trigger bipolar-junction-transistors (BJTs) parasitic under the gate structures to release ESD stress.