Semiconductor device and method of manufacturing the same
AssigneesSeiko Epson Corporation, Tadahiro Ohmi
InventorsTadahiro Ohmi, Hiroyuki Shimada
Life of this patent
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Abstract
A semiconductor device includes an NMOSFET and a PMOSFET. Each MOSFET includes first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like, a channel region formed between the first and second impurity diffusion layers, a gate insulation layer at least formed on the channel region, and agate electrode formed on the gate insulation layer. The gate electrode includes a tantalum nitride layer in a region in contact with at least the gate insulation layer. The semiconductor device exhibits high current drive capability and can be manufactured at high yield.
Claims45
A semiconductor device comprising:
- first and second impurity diffusion layers forming a source region and a drain region which are formed in a semiconductor layer;
- a channel region formed between the first and second impurity diffusion layers;
- a gate insulation layer formed at least on the channel region;
- and
- a gate electrode formed on the gate insulation layer,
- wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer.
A complementary semiconductor device comprising an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor,
- wherein each of the N-channel insulated gate field effect transistor and the P-channel insulated gate field effect transistor includes:
- first and second impurity diffusion layers for forming a source region and a drain region which are formed in a semiconductor layer;
- a channel region formed between the first and second impurity diffusion layers;
- a gate insulation layer formed on the channel region;
- and
- a gate electrode formed on the gate insulation layer, and
- wherein the gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulation layer.
A method of manufacturing a semiconductor device comprising the following steps (a) to (c):
- (a) a step of forming a gate insulation layer on a semiconductor layer;
- (b) a step of forming a gate electrode on the gate insulation layer, and forming a tantalum nitride layer in a region in contact with at least the gate insulation layer;
- and
- (c) a step of forming first and second impurity diffusion layers forming a source region and a drain region by introducing impurities into the semiconductor layer.
A method of manufacturing a complementary semiconductor device including an N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, the method comprising the following steps (a) to (c):
- (a) a step of forming a gate insulation layer on a semiconductor layer;
- (b) a step of forming a gate electrode on the gate insulation layer, and forming a tantalum nitride layer in a region in contact with at least the gate insulation layer;
- and
- (c) a step of introducing impurities into the semiconductor layer to form a source region and a drain region, comprising forming N-type first and second impurity diffusion layers for the N-channel insulated gate field effect transistor and forming P-type first and second impurity diffusion layers for the P-channel insulated gate field effect transistor.
Dependencies are inferred from the claim text.